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Searched refs:mv_ddr_speed_bin_timing_get (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_training_db.h36 unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing …
H A Dddr3_training.c520 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get in hws_ddr3_tip_init_controller()
1394 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get in ddr3_tip_freq_set()
1645 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW1K); in ddr3_tip_set_timing()
1649 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW2K); in ddr3_tip_set_timing()
1654 t_pd = GET_MAX_VALUE(t_ckclk * 3, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TPD)); in ddr3_tip_set_timing()
1657 …t_xpdll = GET_MAX_VALUE(t_ckclk * 10, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TXPDL… in ddr3_tip_set_timing()
1660 t_rrd = (page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index, in ddr3_tip_set_timing()
1662 mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD2K); in ddr3_tip_set_timing()
1664 t_rtp = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index, in ddr3_tip_set_timing()
1667 t_wtr = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index, in ddr3_tip_set_timing()
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H A Dddr3_training_db.c413 unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing … in mv_ddr_speed_bin_timing_get() function