| /openbmc/linux/drivers/clk/ |
| H A D | clk-multiplier.c | 15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument
17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl()
18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument
25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
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| H A D | clk-fixed-factor.c | 28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
83 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
105 fix->mult = mult; in __clk_hw_register_fixed_factor()
152 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
155 flags, mult, div, true); in devm_clk_hw_register_fixed_factor_index()
174 unsigned long flags, unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_parent_hw() argument
177 -1, flags, mult, div, true); in devm_clk_hw_register_fixed_factor_parent_hw()
183 unsigned long flags, unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor_parent_hw() argument
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mult.c | 14 unsigned long mult, min, max; member
18 struct _ccu_mult *mult) in ccu_mult_find_best() argument
23 if (_mult < mult->min) in ccu_mult_find_best()
24 _mult = mult->min; in ccu_mult_find_best()
26 if (_mult > mult->max) in ccu_mult_find_best()
27 _mult = mult->max; in ccu_mult_find_best()
29 mult->mult = _mult; in ccu_mult_find_best()
41 _cm.min = cm->mult.min; in ccu_mult_round_rate()
43 if (cm->mult.max) in ccu_mult_round_rate()
44 _cm.max = cm->mult.max; in ccu_mult_round_rate()
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | rcar-gen4-cpg.c | 74 unsigned int mult; in cpg_pll_clk_recalc_rate() local
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; in cpg_pll_clk_recalc_rate()
78 return parent_rate * mult * 2; in cpg_pll_clk_recalc_rate()
84 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
94 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
96 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
104 unsigned int mult; in cpg_pll_clk_set_rate() local
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); in cpg_pll_clk_set_rate()
108 mult = clamp(mult, 1U, 256U); in cpg_pll_clk_set_rate()
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| H A D | rcar-gen3-cpg.c | 56 unsigned int mult; in cpg_pll_clk_recalc_rate() local
60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
69 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
79 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
81 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
89 unsigned int mult, i; in cpg_pll_clk_set_rate() local
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
93 mult = clamp(mult, 1U, 128U); in cpg_pll_clk_set_rate()
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| H A D | rcar-gen2-cpg.c | 57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate()
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
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| H A D | clk-sh73a0.c | 80 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
111 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
115 mult *= 2; in sh73a0_cpg_register_clock()
123 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
124 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
125 mult = 1; in sh73a0_cpg_register_clock()
127 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
153 mult, div); in sh73a0_cpg_register_clock()
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| H A D | clk-rz.c | 51 unsigned mult; in rz_cpg_register_clock() local
58 mult = cpg_mode ? (32 / 4) : 30; in rz_cpg_register_clock()
60 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); in rz_cpg_register_clock()
78 mult = frqcr_tab[val]; in rz_cpg_register_clock()
79 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); in rz_cpg_register_clock()
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-pllv4.c | 82 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local
85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
86 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate()
87 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate()
95 return (parent_rate * mult) + (u32)temp64; in clk_pllv4_recalc_rate()
107 u32 mult; in clk_pllv4_round_rate() local
112 mult = temp64; in clk_pllv4_round_rate()
113 if (mult >= pllv4_mult_range[1] && in clk_pllv4_round_rate()
114 mult <= pllv4_mult_range[0]) { in clk_pllv4_round_rate()
115 round_rate = parent_rate * mult; in clk_pllv4_round_rate()
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| /openbmc/linux/drivers/iio/common/inv_sensors/ |
| H A D | inv_sensors_timestamp.c | 52 ts->mult = chip->init_period / chip->clock_period; in inv_sensors_timestamp_init()
63 uint32_t mult; in inv_sensors_timestamp_update_odr() local
69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr()
70 if (mult != ts->mult) in inv_sensors_timestamp_update_odr()
71 ts->new_mult = mult; in inv_sensors_timestamp_update_odr()
81 static bool inv_validate_period(struct inv_sensors_timestamp *ts, uint32_t period, uint32_t mult) in inv_validate_period() argument
86 period_min = ts->min_period * mult; in inv_validate_period()
87 period_max = ts->max_period * mult; in inv_validate_period()
95 uint32_t mult, uint32_t period) in inv_update_chip_period() argument
99 if (!inv_validate_period(ts, period, mult)) in inv_update_chip_period()
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| /openbmc/linux/drivers/clk/mvebu/ |
| H A D | orion.c | 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
190 *mult = 1; in mv88f5281_get_clk_ratio()
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| H A D | mv98dx3236.c | 118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
126 *mult = mv98dx4251_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
129 *mult = mv98dx3236_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
135 *mult = mv98dx4251_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
138 *mult = mv98dx3236_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sun4i-pll3.c | 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
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| H A D | clk-a10-pll2.c | 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
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| /openbmc/linux/include/linux/ |
| H A D | random.h | 78 u32 mult = ceil * get_random_u8(); in get_random_u32_below() local
79 if (likely(is_power_of_2(ceil) || (u8)mult >= (1U << 8) % ceil)) in get_random_u32_below()
80 return mult >> 8; in get_random_u32_below()
82 u32 mult = ceil * get_random_u16(); in get_random_u32_below() local
83 if (likely(is_power_of_2(ceil) || (u16)mult >= (1U << 16) % ceil)) in get_random_u32_below()
84 return mult >> 16; in get_random_u32_below()
86 u64 mult = (u64)ceil * get_random_u32(); in get_random_u32_below() local
87 if (likely(is_power_of_2(ceil) || (u32)mult >= -ceil % ceil)) in get_random_u32_below()
88 return mult >> 32; in get_random_u32_below()
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_dpllcore.c | 113 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
119 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore()
121 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
123 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
130 if (mult == 1) in omap2_reprogram_dpllcore()
148 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
152 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
156 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
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| /openbmc/linux/sound/core/ |
| H A D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
24 mult = 1000000000; in snd_pcm_timer_resolution_change()
28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change()
29 mult /= l; in snd_pcm_timer_resolution_change()
38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change()
39 mult /= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | am33xx-clocks.dtsi | 23 clock-mult = <1>;
31 clock-mult = <1>;
39 clock-mult = <1>;
47 clock-mult = <1>;
55 clock-mult = <1>;
63 clock-mult = <1>;
71 clock-mult = <1>;
79 clock-mult = <1>;
87 clock-mult = <1>;
95 clock-mult = <1>;
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| H A D | omap36xx-omap3430es2plus-clocks.dtsi | 38 clock-mult = <1>;
54 clock-mult = <1>;
78 clock-mult = <1>;
86 clock-mult = <1>;
94 clock-mult = <1>;
102 clock-mult = <1>;
110 clock-mult = <1>;
118 clock-mult = <1>;
126 clock-mult = <1>;
134 clock-mult = <1>;
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| H A D | am43xx-clocks.dtsi | 39 clock-mult = <1>;
47 clock-mult = <1>;
55 clock-mult = <1>;
63 clock-mult = <1>;
71 clock-mult = <1>;
79 clock-mult = <1>;
87 clock-mult = <1>;
95 clock-mult = <1>;
103 clock-mult = <1>;
321 clock-mult = <1>;
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| /openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/ncp/libowfat/ |
| H A D | 0001-Depend-on-haveuint128.h-for-umult64.c.patch | 7 mult/umult64.c:9:10: fatal error: 'haveuint128.h' file not found
33 @@ -430,7 +430,7 @@ range_str4inbuf.o: mult/range_str4inbuf.c rangecheck.h
34 range_strinbuf.o: mult/range_strinbuf.c rangecheck.h
35 umult16.o: mult/umult16.c uint16.h
36 umult32.o: mult/umult32.c uint32.h
37 -umult64.o: mult/umult64.c uint64.h
38 +umult64.o: mult/umult64.c uint64.h haveuint128.h
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap36xx-omap3430es2plus-clocks.dtsi | 49 clock-mult = <1>;
80 clock-mult = <1>;
103 clock-mult = <1>;
111 clock-mult = <1>;
119 clock-mult = <1>;
127 clock-mult = <1>;
135 clock-mult = <1>;
143 clock-mult = <1>;
151 clock-mult = <1>;
159 clock-mult = <1>;
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| /openbmc/u-boot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen3.c | 163 u32 value, mult, div, prediv, postdiv; in gen3_clk_get_rate64() local
213 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
214 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
216 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
230 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
231 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
233 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
247 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
248 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
250 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
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| /openbmc/linux/drivers/thermal/broadcom/ |
| H A D | brcmstb_thermal.c | 107 unsigned int mult; member
124 int mult = priv->temp_params->mult; in avs_tmon_code_to_temp() local
126 return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult)); in avs_tmon_code_to_temp()
139 int mult = priv->temp_params->mult; in avs_tmon_temp_to_code() local
148 return (u32)(DIV_ROUND_UP(offset - temp, mult)); in avs_tmon_temp_to_code()
150 return (u32)((offset - temp) / mult); in avs_tmon_temp_to_code()
295 .mult = 557,
306 .mult = 487,
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| /openbmc/u-boot/cmd/ |
| H A D | misc.c | 29 uint mult = CONFIG_SYS_HZ / 10; in do_sleep() local
30 for (frpart++; *frpart != '\0' && mult > 0; frpart++) { in do_sleep()
35 mdelay += (*frpart - '0') * mult; in do_sleep()
36 mult /= 10; in do_sleep()
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