Home
last modified time | relevance | path

Searched refs:mtk_ddp_write (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ethdr.c169 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); in mtk_ethdr_layer_config()
189 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, in mtk_ethdr_layer_config()
191 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); in mtk_ethdr_layer_config()
212 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
215 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
218 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
221 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
224 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, in mtk_ethdr_config()
227 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0); in mtk_ethdr_config()
228 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1); in mtk_ethdr_config()
[all …]
H A Dmtk_disp_merge.c88 mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq()
91 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq()
100 mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq()
103 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq()
113 mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN, in mtk_merge_fifo_setting()
156 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
158 mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
160 mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
170 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
173 mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
[all …]
H A Dmtk_disp_ccorr.c63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
124 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], in mtk_ccorr_ctm_set()
126 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], in mtk_ccorr_ctm_set()
128 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], in mtk_ccorr_ctm_set()
130 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], in mtk_ccorr_ctm_set()
132 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, in mtk_ccorr_ctm_set()
H A Dmtk_drm_ddp_comp.c69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write() function
137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); in mtk_dither_set_common()
138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); in mtk_dither_set_common()
139 mtk_ddp_write(cmdq_pkt, in mtk_dither_set_common()
144 mtk_ddp_write(cmdq_pkt, in mtk_dither_set_common()
150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); in mtk_dither_set_common()
160 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE); in mtk_dither_config()
161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, in mtk_dither_config()
226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); in mtk_od_config()
227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); in mtk_od_config()
[all …]
H A Dmtk_disp_ovl.c266 mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, in mtk_ovl_set_bit_depth()
287 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
288 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
340 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
351 mtk_ddp_write(cmdq_pkt, gmc_value, in mtk_ovl_layer_on()
364 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_off()
H A Dmtk_disp_aal.c55 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
56 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
H A Dmtk_disp_color.c66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config()
67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config()
H A Dmtk_mdp_rdma.c175 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
176 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
H A Dmtk_disp_rdma.c213 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); in mtk_rdma_config()
288 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
H A Dmtk_disp_gamma.c108 mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, in mtk_gamma_config()
H A Dmtk_drm_ddp_comp.h285 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,