Searched refs:msr_base (Results 1 – 4 of 4) sorted by relevance
147 static void run_and_measure_loop(uint32_t msr_base) in run_and_measure_loop() argument149 const uint64_t branches_retired = rdmsr(msr_base + 0); in run_and_measure_loop()150 const uint64_t insn_retired = rdmsr(msr_base + 1); in run_and_measure_loop()154 pmc_results.branches_retired = rdmsr(msr_base + 0) - branches_retired; in run_and_measure_loop()155 pmc_results.instructions_retired = rdmsr(msr_base + 1) - insn_retired; in run_and_measure_loop()498 static void masked_events_guest_test(uint32_t msr_base) in masked_events_guest_test() argument504 const uint64_t loads = rdmsr(msr_base + 0); in masked_events_guest_test()505 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test()506 const uint64_t loads_stores = rdmsr(msr_base + 2); in masked_events_guest_test()515 pmc_results.loads = rdmsr(msr_base + 0) - loads; in masked_events_guest_test()[all …]
74 .msr_base = MSR_IA32_L3_CBM_BASE,88 .msr_base = MSR_IA32_L2_CBM_BASE,308 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in mba_wrmsr_amd()335 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r)); in mba_wrmsr_intel()346 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); in cat_wrmsr()877 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; in rdt_init_res_defs_intel()897 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; in rdt_init_res_defs_amd()900 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; in rdt_init_res_defs_amd()
404 unsigned int msr_base; member
46 u32 msr_base; member156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()453 uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL; in amd_uncore_cpu_up_prepare()471 uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL; in amd_uncore_cpu_up_prepare()