/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_mpc.c | 44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name 165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc() 167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc() 223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default() 225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default() 251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field() 253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field() 255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field() 257 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field() 259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field() [all …]
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H A D | dcn20_mpc.h | 267 const struct dcn20_mpc_mask *mpc_mask; member 274 const struct dcn20_mpc_mask *mpc_mask,
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H A D | dcn20_resource.c | 496 static const struct dcn20_mpc_mask mpc_mask = { variable 850 &mpc_mask, in dcn20_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_mpc.c | 40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name 107 const struct dcn201_mpc_mask *mpc_mask, in dcn201_mpc_construct() argument 118 mpc201->mpc_mask = mpc_mask; in dcn201_mpc_construct()
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H A D | dcn201_mpc.h | 76 const struct dcn201_mpc_mask *mpc_mask; member 83 const struct dcn201_mpc_mask *mpc_mask,
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H A D | dcn201_resource.c | 497 static const struct dcn201_mpc_mask mpc_mask = { variable 733 &mpc_mask, in dcn201_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_mpc.c | 41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name 180 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field() 182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field() 185 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field() 187 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field() 189 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field() 191 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field() 194 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field() 196 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field() 198 reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field() [all …]
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H A D | dcn30_mpc.h | 999 const struct dcn30_mpc_mask *mpc_mask; member 1007 const struct dcn30_mpc_mask *mpc_mask,
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H A D | dcn30_resource.c | 553 static const struct dcn30_mpc_mask mpc_mask = { variable 850 &mpc_mask, in dcn30_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_mpc.c | 42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name 53 …if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_P… in mpc32_mpc_init() 60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc32_mpc_init() 143 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; in mpc32_post1dlut_get_reg_field() 145 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc32_post1dlut_get_reg_field() 147 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; in mpc32_post1dlut_get_reg_field() 149 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc32_post1dlut_get_reg_field() 152 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; in mpc32_post1dlut_get_reg_field() 154 reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; in mpc32_post1dlut_get_reg_field() 156 reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; in mpc32_post1dlut_get_reg_field() [all …]
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H A D | dcn32_mpc.h | 331 const struct dcn30_mpc_mask *mpc_mask,
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H A D | dcn32_resource.c | 463 static const struct dcn30_mpc_mask mpc_mask = { variable 957 &mpc_mask, in dcn32_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_mpc.c | 37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name 518 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct() argument 529 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
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H A D | dcn10_mpc.h | 131 const struct dcn_mpc_mask *mpc_mask; member 138 const struct dcn_mpc_mask *mpc_mask,
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H A D | dcn10_resource.c | 383 static const struct dcn_mpc_mask mpc_mask = { variable 686 &mpc_mask, in dcn10_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
H A D | dcn302_resource.c | 642 static const struct dcn30_mpc_mask mpc_mask = { variable 653 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
H A D | dcn303_resource.c | 588 static const struct dcn30_mpc_mask mpc_mask = { variable 599 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
H A D | dcn301_resource.c | 528 static const struct dcn30_mpc_mask mpc_mask = { variable 804 &mpc_mask, in dcn301_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
H A D | dcn21_resource.c | 295 static const struct dcn20_mpc_mask mpc_mask = { variable 1092 &mpc_mask, in dcn21_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/ |
H A D | dcn316_resource.c | 600 static const struct dcn30_mpc_mask mpc_mask = { variable 1008 &mpc_mask, in dcn31_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/ |
H A D | dcn315_resource.c | 603 static const struct dcn30_mpc_mask mpc_mask = { variable 1012 &mpc_mask, in dcn31_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/ |
H A D | dcn321_resource.c | 463 static const struct dcn30_mpc_mask mpc_mask = { variable 956 &mpc_mask, in dcn321_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_resource.c | 610 static const struct dcn30_mpc_mask mpc_mask = { variable 1086 &mpc_mask, in dcn31_mpc_create()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_resource.c | 604 static const struct dcn30_mpc_mask mpc_mask = { variable 1014 &mpc_mask, in dcn31_mpc_create()
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