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Searched refs:mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_offset.h145 #define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_offset.h11722 #define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX … macro