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Searched refs:mmSDMA1_PHASE2_QUANTUM (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_offset.h164 #define mmSDMA1_PHASE2_QUANTUM 0x004f macro
H A Dsdma1_4_2_offset.h164 #define mmSDMA1_PHASE2_QUANTUM … macro
H A Dsdma1_4_2_2_offset.h164 #define mmSDMA1_PHASE2_QUANTUM … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h1146 #define mmSDMA1_PHASE2_QUANTUM … macro
H A Dgc_10_3_0_offset.h1186 #define mmSDMA1_PHASE2_QUANTUM … macro