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Searched refs:mmRLC_SERDES_WR_NONCU_MASTER_MASK (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c3533 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
3587 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3638 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
H A Dgfx_v8_0.c5487 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h1315 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e macro
H A Dgfx_7_0_d.h1302 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e macro
H A Dgfx_8_1_d.h1413 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e macro
H A Dgfx_8_0_d.h1415 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6083 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK … macro
H A Dgc_9_1_offset.h6305 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK … macro
H A Dgc_9_2_1_offset.h6283 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK … macro