/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_9_4_1_offset.h | 40 #define mmGRBM_SOFT_RESET … macro
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H A D | gc_9_0_offset.h | 47 #define mmGRBM_SOFT_RESET … macro
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H A D | gc_9_1_offset.h | 47 #define mmGRBM_SOFT_RESET … macro
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H A D | gc_9_2_1_offset.h | 47 #define mmGRBM_SOFT_RESET … macro
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H A D | gc_10_1_0_offset.h | 2053 #define mmGRBM_SOFT_RESET … macro
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H A D | gc_10_3_0_offset.h | 2134 #define mmGRBM_SOFT_RESET … macro
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v5_2.c | 718 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset() 721 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset() 722 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset() 727 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in sdma_v5_2_soft_reset() 728 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in sdma_v5_2_soft_reset()
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H A D | gfx_v7_0.c | 3426 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset() 3429 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_rlc_reset() 3432 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_rlc_reset() 4628 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset() 4631 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset() 4632 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset() 4637 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset() 4638 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
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H A D | gfx_v8_0.c | 5053 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset() 5056 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset() 5057 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset() 5062 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset() 5063 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
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H A D | gfx_v9_0.c | 3904 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset() 3907 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_soft_reset() 3908 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset() 3913 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v9_0_soft_reset() 3914 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v9_0_soft_reset()
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H A D | gfx_v10_0.c | 7287 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset() 7290 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_soft_reset() 7291 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset() 7296 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_soft_reset() 7297 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_6_0_d.h | 776 #define mmGRBM_SOFT_RESET 0x2008 macro
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H A D | gfx_7_2_d.h | 793 #define mmGRBM_SOFT_RESET 0x2008 macro
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H A D | gfx_7_0_d.h | 780 #define mmGRBM_SOFT_RESET 0x2008 macro
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H A D | gfx_8_1_d.h | 867 #define mmGRBM_SOFT_RESET 0x2008 macro
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H A D | gfx_8_0_d.h | 868 #define mmGRBM_SOFT_RESET 0x2008 macro
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/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | fiji_smumgr.c | 215 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in fiji_start_avfs_btc() 217 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in fiji_start_avfs_btc()
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H A D | polaris10_smumgr.c | 113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc() 114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
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