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Searched refs:mmGDS_VMID0_SIZE (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c2342 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v9_0_init_compute_vmid()
2360 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v9_0_init_gds_vmid()
4049 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4316 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()
4341 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); in gfx_v9_0_do_edc_gds_workarounds()
H A Dgfx_v7_0.c94 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
5087 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
H A Dgfx_v10_0.c4858 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
4879 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
7377 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
H A Dgfx_v8_0.c179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
7064 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h2255 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_7_0_d.h2233 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_8_1_d.h2432 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_8_0_d.h2453 #define mmGDS_VMID0_SIZE 0x3301 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3045 #define mmGDS_VMID0_SIZE … macro
H A Dgc_9_1_offset.h3275 #define mmGDS_VMID0_SIZE … macro
H A Dgc_9_2_1_offset.h3225 #define mmGDS_VMID0_SIZE … macro
H A Dgc_10_1_0_offset.h5543 #define mmGDS_VMID0_SIZE … macro
H A Dgc_10_3_0_offset.h5170 #define mmGDS_VMID0_SIZE … macro