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Searched refs:mmCP_SEM_WAIT_TIMER (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h544 #define mmCP_SEM_WAIT_TIMER 0x216F macro
H A Dgfx_7_2_d.h455 #define mmCP_SEM_WAIT_TIMER 0xc06f macro
H A Dgfx_7_0_d.h443 #define mmCP_SEM_WAIT_TIMER 0xc06f macro
H A Dgfx_8_1_d.h493 #define mmCP_SEM_WAIT_TIMER 0xc06f macro
H A Dgfx_8_0_d.h493 #define mmCP_SEM_WAIT_TIMER 0xc06f macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2056 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v6_0_cp_gfx_resume()
H A Dgfx_v7_0.c2535 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v7_0_cp_gfx_resume()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h4725 #define mmCP_SEM_WAIT_TIMER … macro
H A Dgc_9_1_offset.h4955 #define mmCP_SEM_WAIT_TIMER … macro
H A Dgc_9_2_1_offset.h4911 #define mmCP_SEM_WAIT_TIMER … macro
H A Dgc_10_1_0_offset.h7217 #define mmCP_SEM_WAIT_TIMER … macro
H A Dgc_10_3_0_offset.h6844 #define mmCP_SEM_WAIT_TIMER … macro