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Searched refs:mmCP_RB0_CNTL (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h54 { 0x0840800a, mmCP_RB0_CNTL },
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h495 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_7_2_d.h201 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_7_0_d.h201 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_8_1_d.h226 #define mmCP_RB0_CNTL 0x3041 macro
H A Dgfx_8_0_d.h225 #define mmCP_RB0_CNTL 0x3041 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2074 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
2077 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_gfx_resume()
2089 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v6_0_cp_gfx_resume()
H A Dgfx_v7_0.c2555 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
2558 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v7_0_cp_gfx_resume()
2571 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
H A Dgfx_v8_0.c4260 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v8_0_cp_gfx_resume()
4263 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v8_0_cp_gfx_resume()
4276 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3118 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
3135 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v10_0.c6107 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
6127 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2366 #define mmCP_RB0_CNTL … macro
H A Dgc_9_1_offset.h2643 #define mmCP_RB0_CNTL … macro
H A Dgc_9_2_1_offset.h2581 #define mmCP_RB0_CNTL … macro
H A Dgc_10_1_0_offset.h4711 #define mmCP_RB0_CNTL … macro
H A Dgc_10_3_0_offset.h4366 #define mmCP_RB0_CNTL … macro