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Searched refs:mmCP_PQ_WPTR_POLL_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h264 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 macro
H A Dgfx_7_0_d.h262 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 macro
H A Dgfx_8_1_d.h295 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 macro
H A Dgfx_8_0_d.h295 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2982 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_mqd_commit()
2984 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); in gfx_v7_0_mqd_commit()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2497 #define mmCP_PQ_WPTR_POLL_CNTL … macro
H A Dgc_9_1_offset.h2771 #define mmCP_PQ_WPTR_POLL_CNTL … macro
H A Dgc_9_2_1_offset.h2707 #define mmCP_PQ_WPTR_POLL_CNTL … macro
H A Dgc_10_1_0_offset.h4835 #define mmCP_PQ_WPTR_POLL_CNTL … macro
H A Dgc_10_3_0_offset.h4496 #define mmCP_PQ_WPTR_POLL_CNTL … macro