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Searched refs:mmCP_ME_CNTL (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h51 { 0x15000000, mmCP_ME_CNTL },
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h447 #define mmCP_ME_CNTL 0x21B6 macro
H A Dgfx_7_2_d.h518 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_7_0_d.h505 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_8_1_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
H A Dgfx_8_0_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2366 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2368 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v7_0_cp_gfx_enable()
4622 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
H A Dgfx_v6_0.c1918 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable()
1920 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
H A Dgfx_v10_0.c5658 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v10_0_cp_gfx_enable()
5665 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
5667 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
H A Dgfx_v8_0.c4096 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable()
4107 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
H A Dgfx_v9_0.c2961 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable()
2966 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h197 #define mmCP_ME_CNTL … macro
H A Dgc_9_1_offset.h197 #define mmCP_ME_CNTL … macro
H A Dgc_9_2_1_offset.h191 #define mmCP_ME_CNTL … macro
H A Dgc_10_1_0_offset.h2199 #define mmCP_ME_CNTL … macro
H A Dgc_10_3_0_offset.h2282 #define mmCP_ME_CNTL … macro