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Searched refs:mmCP_MEC_ME2_UCODE_ADDR (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h254 #define mmCP_MEC_ME2_UCODE_ADDR 0x305e macro
H A Dgfx_7_0_d.h252 #define mmCP_MEC_ME2_UCODE_ADDR 0x305e macro
H A Dgfx_8_1_d.h284 #define mmCP_MEC_ME2_UCODE_ADDR 0xf81c macro
H A Dgfx_8_0_d.h283 #define mmCP_MEC_ME2_UCODE_ADDR 0xf81c macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2691 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2694 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6751 #define mmCP_MEC_ME2_UCODE_ADDR … macro
H A Dgc_9_1_offset.h6975 #define mmCP_MEC_ME2_UCODE_ADDR … macro
H A Dgc_9_2_1_offset.h7003 #define mmCP_MEC_ME2_UCODE_ADDR … macro
H A Dgc_10_1_0_offset.h10249 #define mmCP_MEC_ME2_UCODE_ADDR … macro
H A Dgc_10_3_0_offset.h9969 #define mmCP_MEC_ME2_UCODE_ADDR … macro