Searched refs:mmCP_HQD_PQ_WPTR_POLL_ADDR (Results 1 – 16 of 16) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 1509 { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
1519 { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
1529 { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
1539 { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v10_3.c | 253 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in hqd_load_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 267 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_hqd_load()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 282 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_hqd_load()
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| H A D | mes_v10_1.c | 781 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
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| H A D | gfx_v9_0.c | 3447 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v9_0_kiq_init_register()
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| H A D | gfx_v10_0.c | 6685 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v10_0_kiq_init_register()
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_2_d.h | 593 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 macro
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| H A D | gfx_7_0_d.h | 580 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 macro
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| H A D | gfx_8_1_d.h | 643 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 macro
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| H A D | gfx_8_0_d.h | 643 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 macro
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2845 #define mmCP_HQD_PQ_WPTR_POLL_ADDR … macro
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| H A D | gc_9_1_offset.h | 3073 #define mmCP_HQD_PQ_WPTR_POLL_ADDR … macro
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| H A D | gc_9_2_1_offset.h | 3029 #define mmCP_HQD_PQ_WPTR_POLL_ADDR … macro
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| H A D | gc_10_1_0_offset.h | 5327 #define mmCP_HQD_PQ_WPTR_POLL_ADDR … macro
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| H A D | gc_10_3_0_offset.h | 4962 #define mmCP_HQD_PQ_WPTR_POLL_ADDR … macro
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