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Searched refs:mmCP_HQD_PQ_RPTR_REPORT_ADDR (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v10_1.c772 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
H A Dgfx_v9_0.c3441 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v9_0_kiq_init_register()
H A Dgfx_v10_0.c6679 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v10_0_kiq_init_register()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h591 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 macro
H A Dgfx_7_0_d.h578 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 macro
H A Dgfx_8_1_d.h641 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 macro
H A Dgfx_8_0_d.h641 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2841 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … macro
H A Dgc_9_1_offset.h3069 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … macro
H A Dgc_9_2_1_offset.h3025 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … macro
H A Dgc_10_1_0_offset.h5323 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … macro
H A Dgc_10_3_0_offset.h4958 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR … macro