Searched refs:mmCP_CPC_IC_BASE_LO (Results 1 – 11 of 11) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 58 { 0x540ff000, mmCP_CPC_IC_BASE_LO },
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| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | smu8_smumgr.c | 208 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data); in smu8_load_mec_firmware()
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_8_1_d.h | 346 #define mmCP_CPC_IC_BASE_LO 0x30b9 macro
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| H A D | gfx_8_0_d.h | 346 #define mmCP_CPC_IC_BASE_LO 0x30b9 macro
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2603 #define mmCP_CPC_IC_BASE_LO … macro
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| H A D | gc_9_1_offset.h | 2873 #define mmCP_CPC_IC_BASE_LO … macro
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| H A D | gc_9_2_1_offset.h | 2807 #define mmCP_CPC_IC_BASE_LO … macro
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| H A D | gc_10_1_0_offset.h | 10277 #define mmCP_CPC_IC_BASE_LO … macro
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| H A D | gc_10_3_0_offset.h | 9999 #define mmCP_CPC_IC_BASE_LO … macro
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v10_0.c | 5604 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
6276 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
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| H A D | gfx_v9_0.c | 3201 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, in gfx_v9_0_cp_compute_load_microcode()
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