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Searched refs:mmCB_BLEND5_CONTROL (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h154 #define mmCB_BLEND5_CONTROL 0xA1E5 macro
H A Dgfx_7_2_d.h37 #define mmCB_BLEND5_CONTROL 0xa1e5 macro
H A Dgfx_7_0_d.h37 #define mmCB_BLEND5_CONTROL 0xa1e5 macro
H A Dgfx_8_1_d.h38 #define mmCB_BLEND5_CONTROL 0xa1e5 macro
H A Dgfx_8_0_d.h38 #define mmCB_BLEND5_CONTROL 0xa1e5 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3977 #define mmCB_BLEND5_CONTROL … macro
H A Dgc_9_1_offset.h4207 #define mmCB_BLEND5_CONTROL … macro
H A Dgc_9_2_1_offset.h4159 #define mmCB_BLEND5_CONTROL … macro
H A Dgc_10_1_0_offset.h6379 #define mmCB_BLEND5_CONTROL … macro
H A Dgc_10_3_0_offset.h6010 #define mmCB_BLEND5_CONTROL … macro