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Searched refs:min_clocks (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1620 struct PP_Clocks min_clocks = {0}; in vega12_notify_smc_display_config_after_ps_adjustment() local
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1636 clock_req.clock_freq_in_khz = min_clocks.dcefClock / 10; in vega12_notify_smc_display_config_after_ps_adjustment()
1642 min_clocks.dcefClockInSR / 100, in vega12_notify_smc_display_config_after_ps_adjustment()
H A Dvega20_hwmgr.c2354 struct PP_Clocks min_clocks = {0}; in vega20_notify_smc_display_config_after_ps_adjustment() local
2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2364 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2369 min_clocks.dcefClockInSR / 100, in vega20_notify_smc_display_config_after_ps_adjustment()
2379 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()
H A Dvega10_hwmgr.c4101 struct PP_Clocks min_clocks = {0}; in vega10_notify_smc_display_config_after_ps_adjustment() local
4112 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4113 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4114 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
4117 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) in vega10_notify_smc_display_config_after_ps_adjustment()
4127 min_clocks.dcefClockInSR / 100, in vega10_notify_smc_display_config_after_ps_adjustment()
4136 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()
4137 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); in vega10_notify_smc_display_config_after_ps_adjustment()
H A Dsmu7_hwmgr.c4091 struct PP_Clocks min_clocks = {0}; in smu7_find_dpm_states_clocks_in_dpm_table() local
4108 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && in smu7_find_dpm_states_clocks_in_dpm_table()
4109 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || in smu7_find_dpm_states_clocks_in_dpm_table()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c2095 struct smu_clocks min_clocks = {0}; in navi10_notify_smc_display_config() local
2099 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()
2100 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()
2101 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
2105 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
2112 min_clocks.dcef_clock_in_sr/100, in navi10_notify_smc_display_config()
2125 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
H A Dsienna_cichlid_ppt.c1780 struct smu_clocks min_clocks = {0}; in sienna_cichlid_notify_smc_display_config() local
1784 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1785 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1786 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1790 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in sienna_cichlid_notify_smc_display_config()
1797 min_clocks.dcef_clock_in_sr/100, in sienna_cichlid_notify_smc_display_config()
1810 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()