| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 329 if (max_clk_limit->memclk_mhz != 0) in override_max_clk_values()
330 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz; in override_max_clk_values()
369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) in build_synthetic_soc_states()
370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
380 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { in build_synthetic_soc_states()
382 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()
457 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; in build_synthetic_soc_states()
495 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16) in build_synthetic_soc_states()
505 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16; in build_synthetic_soc_states()
524 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { in build_synthetic_soc_states()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 270 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_update_clocks()
368 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_set_hard_min_memclk()
371 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
384 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_set_hard_max_memclk()
387 static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn3_set_max_memclk() argument
394 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_max_memclk()
396 static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn3_set_min_memclk() argument
402 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_min_memclk()
416 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, in dcn3_get_memclk_states_from_smu()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
262 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn302_fpu_update_bw_bounding_box()
273 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
256 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn303_fpu_update_bw_bounding_box()
267 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
284 bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
299 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 88 unsigned int memclk_mhz; member
290 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
291 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
233 …mmy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
235 …mmy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
237 …mmy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
239 …mmy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
2167 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; in dcn32_calculate_wm_and_dlg_fpu()
2328 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) in dcn32_patch_dpm_table()
2329 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in dcn32_patch_dpm_table()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 822 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn32_set_hard_min_memclk()
849 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, in dcn32_get_memclk_states_from_smu()
851 …clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_get_memclk_states_from_smu()
852 …lk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz; in dcn32_get_memclk_states_from_smu()
868 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; in dcn32_get_memclk_states_from_smu()
921 static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn32_set_max_memclk() argument
928 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn32_set_max_memclk()
931 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn32_set_min_memclk() argument
938 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn32_set_min_memclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 499 .memclk_mhz = 800,
506 .memclk_mhz = 1600,
513 .memclk_mhz = 1067,
520 .memclk_mhz = 1600,
588 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
593 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 583 .memclk_mhz = 800,
590 .memclk_mhz = 1600,
597 .memclk_mhz = 1067,
604 .memclk_mhz = 1600,
667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 512 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
524 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
543 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 623 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
639 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 240 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) in dcn314_update_bw_bounding_box_fpu()
241 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn314_update_bw_bounding_box_fpu()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 624 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box()
692 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box()
776 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2117 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2155 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn30_update_bw_bounding_box()
2168 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2184 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2199 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
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| H A D | dcn30_hwseq.c | 989 …k_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn30_prepare_bandwidth()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 491 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; in dcn30_fpu_calculate_wm_and_dlg()
734 uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; in dcn3_fpu_build_wm_range_table()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn316_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 4747 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) in blank_and_force_memclk() argument
4770 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()
4771 dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()
4812 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM) in dc_enable_dcmode_clk_limit()
4813 maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz; in dc_enable_dcmode_clk_limit()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2381 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; in construct_low_pstate_lvl()
2434 s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn21_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 744 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn32_initialize_min_clocks()
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