Searched refs:mctl_com (Results 1 – 7 of 7) sorted by relevance
/openbmc/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun8i_a23.c | 94 struct sunxi_mctl_com_reg * const mctl_com = in mctl_init() local 226 setbits_le32(&mctl_com->ccr, 0x80000); in mctl_init() 268 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local 287 &mctl_com->cr); in sunxi_dram_init() 288 setbits_le32(&mctl_com->swonr, 0x0003ffff); in sunxi_dram_init() 294 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, in sunxi_dram_init() 302 &mctl_com->cr); in sunxi_dram_init() 303 setbits_le32(&mctl_com->swonr, 0x0003ffff); in sunxi_dram_init() 307 writel(0x00000008, &mctl_com->mcr0_0); in sunxi_dram_init() 308 writel(0x0001000d, &mctl_com->mcr1_0); in sunxi_dram_init() [all …]
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H A D | dram_sun6i.c | 104 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local 176 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_channel_init() 264 struct sunxi_mctl_com_reg * const mctl_com = in mctl_com_init() local 274 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); in mctl_com_init() 277 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init() 295 struct sunxi_mctl_com_reg * const mctl_com = in mctl_port_cfg() local 304 writel(0x00400302, &mctl_com->rmcr[0]); in mctl_port_cfg() 305 writel(0x01000307, &mctl_com->rmcr[1]); in mctl_port_cfg() 306 writel(0x00400302, &mctl_com->rmcr[2]); in mctl_port_cfg() 307 writel(0x01000307, &mctl_com->rmcr[3]); in mctl_port_cfg() [all …]
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H A D | dram_sunxi_dw.c | 89 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port() local 101 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port() 102 writel(cfg1, &mctl_com->mcr[port][1]); in mbus_configure_port() 111 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_h3() local 115 writel((1 << 16) | (400 << 0), &mctl_com->bwcr); in mctl_set_master_priority_h3() 118 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_h3() 136 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority_a64() local 140 writel(399, &mctl_com->tmr); in mctl_set_master_priority_a64() 141 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_a64() 158 writel(0x81000004, &mctl_com->mdfs_bwlr[2]); in mctl_set_master_priority_a64() [all …]
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H A D | dram_sun50i_h6.c | 124 struct sunxi_mctl_com_reg * const mctl_com = in mbus_configure_port() local 136 writel(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port() 137 writel(cfg1, &mctl_com->master[port].cfg1); in mbus_configure_port() 146 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_master_priority() local 150 writel(399, &mctl_com->tmr); in mctl_set_master_priority() 151 writel(BIT(16), &mctl_com->bwcr); in mctl_set_master_priority() 295 struct sunxi_mctl_com_reg * const mctl_com = in mctl_sys_init() local 323 writel(0, &mctl_com->maer0); in mctl_sys_init() 324 writel(0, &mctl_com->maer1); in mctl_sys_init() 325 writel(0, &mctl_com->maer2); in mctl_sys_init() [all …]
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H A D | dram_sun8i_a33.c | 34 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr() local 43 &mctl_com->cr); in mctl_set_cr() 205 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local 289 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init() 300 struct sunxi_mctl_com_reg * const mctl_com = in mctl_sys_init() local 320 writel(0x0, &mctl_com->mapr); in mctl_sys_init() 329 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local 351 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()
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H A D | dram_sun9i.c | 202 struct sunxi_mctl_com_reg * const mctl_com = in mctl_sys_init() local 300 setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30)); in mctl_sys_init() 301 writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */ in mctl_sys_init() 330 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN); in mctl_sys_init() 333 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in mctl_sys_init() 335 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_sys_init() 340 struct sunxi_mctl_com_reg * const mctl_com = in mctl_com_init() local 350 &mctl_com->cr); in mctl_com_init() 352 debug("CR: %d\n", readl(&mctl_com->cr)); in mctl_com_init() 825 struct sunxi_mctl_com_reg * const mctl_com = in DRAMC_get_dram_size() local [all …]
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H A D | dram_sun8i_a83t.c | 33 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr() local 42 &mctl_com->cr); in mctl_set_cr() 261 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local 270 writel(0x000101a0, &mctl_com->bwcr); in mctl_channel_init() 272 writel(0x1, &mctl_com->mapr); in mctl_channel_init() 326 if (readl(&mctl_com->cr) & 0x1) in mctl_channel_init() 383 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init() 427 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local 461 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()
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