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Searched refs:mclk_mask (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/sound/hda/
H A Dintel-nhlt.c176 int mclk_mask = 0; in intel_nhlt_ssp_mclk_mask() local
223 mclk_mask |= blob[mdivc_offset] & GENMASK(1, 0); in intel_nhlt_ssp_mclk_mask()
232 if (hweight_long(mclk_mask) != 1) in intel_nhlt_ssp_mclk_mask()
235 return mclk_mask; in intel_nhlt_ssp_mclk_mask()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c253 uint32_t *mclk_mask, in renoir_get_profiling_clk_mask() argument
261 if (mclk_mask) in renoir_get_profiling_clk_mask()
263 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
269 if (mclk_mask) in renoir_get_profiling_clk_mask()
271 *mclk_mask = 0; in renoir_get_profiling_clk_mask()
286 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
320 &mclk_mask, in renoir_get_dpm_ultimate_freq()
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
935 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
1017 &mclk_mask, in renoir_set_performance_level()
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/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c837 uint32_t *mclk_mask, in vangogh_get_profiling_clk_mask() argument
844 if (mclk_mask) in vangogh_get_profiling_clk_mask()
845 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; in vangogh_get_profiling_clk_mask()
853 if (mclk_mask) in vangogh_get_profiling_clk_mask()
854 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
868 if (mclk_mask) in vangogh_get_profiling_clk_mask()
869 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
928 uint32_t mclk_mask; in vangogh_get_dpm_ultimate_freq() local
972 &mclk_mask, in vangogh_get_dpm_ultimate_freq()
981 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in vangogh_get_dpm_ultimate_freq()
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/openbmc/linux/sound/soc/sof/intel/
H A Dhda.c1660 int mclk_mask; in hda_machine_select() local
1686 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); in hda_machine_select()
1688 if (mclk_mask < 0) { in hda_machine_select()
1693 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); in hda_machine_select()
1695 if (mclk_mask) { in hda_machine_select()
1696 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); in hda_machine_select()
1698 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; in hda_machine_select()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1728 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1736 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1743 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1750 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1753 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1783 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1800 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1804 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
H A Dvega20_hwmgr.c2534 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2542 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2549 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2556 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2559 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2734 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2753 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2757 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
H A Dsmu7_hwmgr.c3168 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
3186 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3189 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
3225 *mclk_mask = 0; in smu7_get_profiling_clk()
3227 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3239 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
3256 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3260 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
H A Dvega10_hwmgr.c4215 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4225 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4231 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4241 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4333 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4350 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4354 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()