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Searched refs:mbar_writeLong (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c68 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()
71 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); in dram_init()
74 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()
79 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
83 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
/openbmc/u-boot/board/freescale/m5253demo/
H A Dm5253demo.c42 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()
48 mbar_writeLong(MCFSIM_DMR0, temp | 1); in dram_init()
51 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()
61 mbar_writeLong(MCFSIM_DACR0, in dram_init()
69 mbar_writeLong(MCFSIM_DACR0, in dram_init()
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dinterrupts.c88 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); in dtimer_intr_setup()
H A Dcpu_init.c265 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); in cpu_init_f()
268 mbar_writeLong(MCF_FMPLL_SYNCR, in cpu_init_f()
694 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); in cpu_init_f()
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h18 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro
H A Dm5271.h17 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro