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Searched refs:max_backends_per_se (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atomfirmware.c794 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
812 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
833 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
H A Dgfx_v6_0.c1321 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()
1455 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()
1474 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()
1576 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1593 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1610 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1627 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()
1644 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
H A Dgfx_v7_0.c1596 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1756 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1774 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
4221 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4238 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4254 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4274 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
H A Damdgpu_gfx.h192 unsigned max_backends_per_se; member
H A Dgfx_v8_0.c1666 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1683 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1730 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1746 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1781 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
3436 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3598 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3616 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
H A Damdgpu_atombios.c729 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
H A Damdgpu_discovery.c1440 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1474 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
H A Damdgpu_kms.c823 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
H A Damdgpu_debugfs.c892 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
H A Dgfx_v11_0.c1589 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * in gfx_v11_0_get_rb_active_bitmap()
1612 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / in gfx_v11_0_setup_rb()
H A Dgfx_v9_0.c2256 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
2267 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
H A Damdgpu_device.c1968 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
H A Dgfx_v10_0.c4728 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
4740 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dni.c897 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
935 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
949 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
963 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
970 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
1091 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1095 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1125 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1137 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
H A Dradeon_kms.c358 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()
361 *value = rdev->config.si.max_backends_per_se * in radeon_info_ioctl()
364 *value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()
H A Dsi.c3103 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3120 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3138 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3155 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()
3172 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()
3289 rdev->config.si.max_backends_per_se); in si_gpu_init()
H A Dradeon.h2089 unsigned max_backends_per_se; member
2128 unsigned max_backends_per_se; member
2159 unsigned max_backends_per_se; member
H A Dcik.c2330 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()
3182 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()
3199 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()
3215 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()
3235 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()
3337 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h1760 uint8_t max_backends_per_se; member
1780 uint8_t max_backends_per_se; member
1805 uint8_t max_backends_per_se; member
1840 uint8_t max_backends_per_se; member
1881 uint8_t max_backends_per_se; member
H A Datombios.h5656 UCHAR max_backends_per_se; member
5669 UCHAR max_backends_per_se; member