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Searched refs:mac_base (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/usb/mtu3/
H A Dmtu3_core.c75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
178 void __iomem *mbase = mtu->mac_base; in mtu3_intr_status_clear()
196 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0); in mtu3_intr_disable()
198 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0); in mtu3_intr_disable()
205 void __iomem *mbase = mtu->mac_base; in mtu3_intr_enable()
234 void __iomem *mbase = mtu->mac_base; in mtu3_set_speed()
274 void __iomem *mbase = mtu->mac_base; in mtu3_csr_init()
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H A Dmtu3_gadget_ep0.c82 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_write_fifo()
102 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_read_fifo()
138 void __iomem *mbase = mtu->mac_base; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
158 void __iomem *mbase = mtu->mac_base; in ep0_do_status_stage()
278 void __iomem *mbase = mtu->mac_base; in handle_test_mode()
328 void __iomem *mbase = mtu->mac_base; in ep0_handle_feature_dev()
443 void __iomem *mbase = mtu->mac_base; in handle_standard_request()
513 void __iomem *mbase = mtu->mac_base; in ep0_rx_state()
596 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_tx_state()
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H A Dmtu3_qmu.c192 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_resume()
334 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_start()
378 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_stop()
429 void __iomem *mbase = mtu->mac_base; in qmu_tx_zlp_error_handler()
482 cur_gpd_dma = read_rxq_cur_addr(mtu->mac_base, epnum); in qmu_error_rx()
512 void __iomem *mbase = mtu->mac_base; in qmu_done_tx()
552 void __iomem *mbase = mtu->mac_base; in qmu_done_rx()
600 void __iomem *mbase = mtu->mac_base; in qmu_exception_isr()
644 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_isr()
H A Dmtu3_gadget.c432 return (int)mtu3_readl(mtu->mac_base, U3D_USB20_FRAME_NUM); in mtu3_gadget_get_frame()
437 mtu3_writel(mtu->mac_base, U3D_DEV_NOTIF_0, in function_wake_notif()
439 mtu3_setbits(mtu->mac_base, U3D_DEV_NOTIF_0, SEND_DEV_NOTIF); in function_wake_notif()
459 mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT); in mtu3_gadget_wakeup()
468 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
472 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
H A Dmtu3_debugfs.c82 void __iomem *mbase = mtu->mac_base; in mtu3_link_state_show()
170 mtu3_debugfs_regset(mtu, mtu->mac_base, regs, 7, "ep-regs", parent); in mtu3_debugfs_ep_regset()
412 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
416 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
H A Dmtu3.h246 void __iomem *mac_base; member
327 void __iomem *mac_base; member
H A Dmtu3_dr.c24 mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION); in toggle_opstate()
25 mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN); in toggle_opstate()
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-qcom-ethqos.c108 void __iomem *mac_base; member
634 val = readl(ethqos->mac_base + MAC_CTRL_REG); in ethqos_configure_sgmii()
656 writel(val, ethqos->mac_base + MAC_CTRL_REG); in ethqos_configure_sgmii()
799 ethqos->mac_base = stmmac_res.addr; in qcom_ethqos_probe()
/openbmc/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c365 void __iomem *mac_base; member
410 iowrite32(value, ag->mac_base + reg); in ag71xx_wr()
412 (void)ioread32(ag->mac_base + reg); in ag71xx_wr()
417 return ioread32(ag->mac_base + reg); in ag71xx_rr()
424 r = ag->mac_base + reg; in ag71xx_sb()
434 r = ag->mac_base + reg; in ag71xx_cb()
1869 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in ag71xx_probe()
1870 if (!ag->mac_base) in ag71xx_probe()
1959 (unsigned long)ag->mac_base, ndev->irq, in ag71xx_probe()
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dcomminf.h481 uint32_t mac_base; member
H A Dmac.c85 return readl(p_eng->run.mac_base + addr); in mac_reg_read()
121 writel(data, p_eng->run.mac_base + addr); in mac_reg_write()
139 printf("\nMAC%d base 0x%08x", p_eng->run.mac_idx, p_eng->run.mac_base); in dump_mac_ROreg()
H A Dmactest.c684 p_eng->run.mac_base = mac_base_lookup_tbl[p_eng->run.mac_idx]; in setup_running()
/openbmc/linux/drivers/atm/
H A Deni.c1691 void __iomem *mac_base; in get_esi_fpga() local
1694 mac_base = base+EPROM_SIZE-sizeof(struct midway_eprom); in get_esi_fpga()
1695 for (i = 0; i < ESI_LEN; i++) dev->esi[i] = readb(mac_base+(i^3)); in get_esi_fpga()
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c13735 u32 mac_base; in bnx2x_check_half_open_conn() local
13749 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_check_half_open_conn()
13752 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13753 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13756 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13767 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_check_half_open_conn()
13775 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()