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Searched refs:l2cache (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu_init.c525 struct ccsr_cluster_l2 __iomem *l2cache; in enable_cluster_l2() local
545 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); in enable_cluster_l2()
561 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); in enable_cluster_l2()
563 printf("enable l2 for cluster %d %p\n", i, l2cache); in enable_cluster_l2()
565 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); in enable_cluster_l2()
566 while ((in_be32(&l2cache->l2csr0) in enable_cluster_l2()
569 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); in enable_cluster_l2()
585 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; in l2cache_init() local
587 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; in l2cache_init() local
600 cache_ctl = l2cache->l2ctl; in l2cache_init()
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H A Dspl_minimal.c17 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; in cpu_init_f() local
19 out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); in cpu_init_f()
22 out_be32(&l2cache->l2errdis, in cpu_init_f()
26 out_be32(&l2cache->l2ctl, in cpu_init_f()
H A Dcpu_init_early.c88 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; in cpu_init_early_f() local
142 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); in cpu_init_early_f()
144 out_be32(&l2cache->l2errdis, in cpu_init_early_f()
147 out_be32(&l2cache->l2ctl, in cpu_init_early_f()
167 clrbits_be32(&l2cache->l2ctl, in cpu_init_early_f()
170 out_be32(&l2cache->l2srbar0, 0x0); in cpu_init_early_f()
H A Dfdt.c221 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; in l2cache_size() local
222 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; in l2cache_size()
297 struct ccsr_cluster_l2 *l2cache = in ft_fixup_l2cache() local
299 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); in ft_fixup_l2cache()
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi57 next-level-cache = <&l2cache>;
81 next-level-cache = <&l2cache>;
105 next-level-cache = <&l2cache>;
129 next-level-cache = <&l2cache>;
287 l2cache: cache-controller@2010000 { label
/openbmc/qemu/hw/ppc/
H A Dppc440_uc.c73 uint32_t l2cache[8]; member
91 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; in dcr_read_l2sram()
163 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); in l2sram_reset()
164 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; in l2sram_reset()
/openbmc/linux/arch/arm/mach-omap2/
H A Dsoc.h443 OMAP3_HAS_FEATURE(l2cache, L2CACHE)
H A Did.c258 OMAP3_SHOW_FEATURE(l2cache); in omap3_cpuinfo()
/openbmc/linux/
H A DMAINTAINERS12174 F: Documentation/devicetree/bindings/cache/freescale-l2cache.txt