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Searched refs:ixCG_CLKPIN_CNTL (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c95 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
H A Dpolaris_baco.c98 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
H A Dtonga_baco.c104 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvi.c559 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk()
1204 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_program_aspm()
1207 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
1212 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
H A Dcik.c925 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) in cik_get_xclk()
1822 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); in cik_program_aspm()
1825 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h56 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro
H A Dsmu_7_1_1_d.h56 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro
H A Dsmu_7_0_1_d.h57 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro
H A Dsmu_7_1_3_d.h60 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro
H A Dsmu_7_1_2_d.h57 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro
H A Dsmu_7_1_0_d.h56 #define ixCG_CLKPIN_CNTL 0xc05001a0 macro