Home
last modified time | relevance | path

Searched refs:ivpu_dbg (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_fw.c106 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", in ivpu_fw_check_api()
165 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", in ivpu_fw_parse()
189 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", in ivpu_fw_parse()
191 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", in ivpu_fw_parse()
344 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", in ivpu_fw_boot_params_print()
346 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", in ivpu_fw_boot_params_print()
348 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", in ivpu_fw_boot_params_print()
350 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", in ivpu_fw_boot_params_print()
352 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", in ivpu_fw_boot_params_print()
355 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", in ivpu_fw_boot_params_print()
[all …]
H A Divpu_pm.c47 ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address); in ivpu_pm_prepare_warm_boot()
145 ivpu_dbg(vdev, PM, "Suspend..\n"); in ivpu_pm_suspend_cb()
162 ivpu_dbg(vdev, PM, "Suspend done.\n"); in ivpu_pm_suspend_cb()
173 ivpu_dbg(vdev, PM, "Resume..\n"); in ivpu_pm_resume_cb()
182 ivpu_dbg(vdev, PM, "Resume done.\n"); in ivpu_pm_resume_cb()
193 ivpu_dbg(vdev, PM, "Runtime suspend..\n"); in ivpu_pm_runtime_suspend_cb()
196 ivpu_dbg(vdev, PM, "Failed to enter idle, rescheduling suspend, retries left %d\n", in ivpu_pm_runtime_suspend_cb()
216 ivpu_dbg(vdev, PM, "Runtime suspend done.\n"); in ivpu_pm_runtime_suspend_cb()
227 ivpu_dbg(vdev, PM, "Runtime resume..\n"); in ivpu_pm_runtime_resume_cb()
233 ivpu_dbg(vdev, PM, "Runtime resume done.\n"); in ivpu_pm_runtime_resume_cb()
[all …]
H A Divpu_mmu.c255 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
259 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
263 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); in ivpu_mmu_config_check()
274 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
287 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
306 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", in ivpu_mmu_strtab_alloc()
325 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_cmdq_alloc()
344 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_evtq_alloc()
429 ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1); in ivpu_mmu_cmdq_cmd_write()
585 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]); in ivpu_mmu_strtab_link_cd()
[all …]
H A Divpu_hw_reg_io.h74 ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_rd32()
84 ivpu_dbg(vdev, REG, "%s RD: %s (0x%08x) => 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_rd64()
92 ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_wr32()
100 ivpu_dbg(vdev, REG, "%s WR: %s (0x%08x) <= 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_wr64()
111 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val); in ivpu_hw_reg_wr32_index()
H A Divpu_job.c190 ivpu_dbg(vdev, JOB, "Job queue full: ctx %d engine %d db %d head %d tail %d\n", in ivpu_cmdq_push_job()
256 ivpu_dbg(vdev, KREF, "Job get: id %u refcount %u\n", job->job_id, kref_read(&job->ref)); in job_get()
272 ivpu_dbg(vdev, KREF, "Job released: id %u\n", job->job_id); in job_release()
283 ivpu_dbg(vdev, KREF, "Job put: id %u refcount %u\n", job->job_id, kref_read(&job->ref)); in job_put()
315 ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx); in ivpu_create_job()
340 ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d engine %d status 0x%x\n", in ivpu_job_done()
401 ivpu_dbg(vdev, JOB, "Job submitted: id %3u addr 0x%llx ctx %2d engine %d next %d\n", in ivpu_direct_job_submission()
532 ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u buf_count %u\n", in ivpu_submit_ioctl()
574 ivpu_dbg(vdev, JOB, "Started %s\n", __func__); in ivpu_job_done_thread()
597 ivpu_dbg(vdev, JOB, "Stopped %s\n", __func__); in ivpu_job_done_thread()
H A Divpu_drv.c64 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n", in ivpu_file_priv_get()
82 ivpu_dbg(vdev, KREF, "file_priv get by id: ctx %u refcount %u\n", in ivpu_file_priv_get_by_ctx_id()
93 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u\n", file_priv->ctx.id); in file_priv_release()
111 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n", in ivpu_file_priv_put()
261 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", in ivpu_open()
282 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", in ivpu_postclose()
330 ivpu_dbg(vdev, PM, "VPU ready message received successfully\n"); in ivpu_wait_for_ready()
446 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
453 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
H A Divpu_fw_log.c43 ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", log->header_size); in fw_log_ptr()
47 ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", log->size); in fw_log_ptr()
54 ivpu_dbg(vdev, FW_BOOT, in fw_log_ptr()
H A Divpu_hw.h73 ivpu_dbg(vdev, PM, "HW power up\n"); in ivpu_hw_power_up()
90 ivpu_dbg(vdev, PM, "HW power down\n"); in ivpu_hw_power_down()
97 ivpu_dbg(vdev, PM, "HW reset\n"); in ivpu_hw_reset()
H A Divpu_gem.c310 ivpu_dbg(vdev, BO, "remove from ctx: ctx %d vpu_addr 0x%llx allocated %d mmu_mapped %d\n", in ivpu_bo_free_vpu_addr()
410 ivpu_dbg(vdev, BO, "free: ctx %d vpu_addr 0x%llx allocated %d mmu_mapped %d\n", in ivpu_bo_free()
413 ivpu_dbg(vdev, BO, "free: ctx (released) allocated %d mmu_mapped %d\n", in ivpu_bo_free()
440 ivpu_dbg(vdev, BO, "mmap: ctx %u handle %u vpu_addr 0x%llx size %zu type %s", in ivpu_bo_mmap()
555 ivpu_dbg(vdev, BO, "alloc shmem: ctx %u vpu_addr 0x%llx size %zu flags 0x%x\n", in ivpu_bo_create_ioctl()
607 ivpu_dbg(vdev, BO, "alloc internal: ctx 0 vpu_addr 0x%llx size %zu flags 0x%x\n", in ivpu_bo_alloc_internal()
H A Divpu_drv.h72 #define ivpu_dbg(vdev, type, fmt, args...) do { \ macro
81 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
H A Divpu_hw_40xx.c117 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in ivpu_hw_read_platform()
237 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n", in ivpu_pll_drive()
648 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in ivpu_boot_soc_cpu_boot()
715 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n", in ivpu_hw_40xx_info_init()
718 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM); in ivpu_hw_40xx_info_init()
803 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_40xx_ats_print()
1035 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_40xx_irqv_handler()
1062 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE"); in ivpu_hw_40xx_irqb_handler()
H A Divpu_ipc.c36 ivpu_dbg(vdev, IPC, in ivpu_ipc_msg_dump()
47 ivpu_dbg(vdev, JSM, in ivpu_jsm_msg_dump()
238 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); in ivpu_ipc_receive()
415 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); in ivpu_ipc_irq_handler()
H A Divpu_jsm_msg.c29 ivpu_dbg(vdev, JSM, "Doorbell %d registered to context %d\n", db_id, ctx_id); in ivpu_jsm_register_db()
49 ivpu_dbg(vdev, JSM, "Doorbell %d unregistered\n", db_id); in ivpu_jsm_unregister_db()
H A Divpu_hw_37xx.c97 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in ivpu_hw_read_platform()
227 ivpu_dbg(vdev, PM, "Skipping PLL request on %s\n", in ivpu_pll_drive()
240 ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n", in ivpu_pll_drive()
605 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in ivpu_boot_soc_cpu_boot()
926 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_37xx_irqv_handler()
953 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", in ivpu_hw_37xx_irqb_handler()