Searched refs:irq_handler_offset (Results 1 – 2 of 2) sorted by relevance
2552 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_pci_dma_qman() local2601 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_pci_dma_qman()2614 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2616 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2641 u32 irq_handler_offset; in gaudi_init_dma_core() local2656 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_dma_core()2661 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2663 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2731 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_hbm_dma_qman() local2772 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_hbm_dma_qman()[all …]
4963 u32 glbl_prot = QMAN_MAKE_TRUSTED, irq_handler_offset; in gaudi2_init_qman_common() local4968 irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base); in gaudi2_init_qman_common()4969 WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()4970 WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()5013 u32 prot, irq_handler_offset; in gaudi2_init_dma_core() local5024 irq_handler_offset = le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl); in gaudi2_init_dma_core()5027 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()5030 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()10911 u32 irq_handler_offset = le32_to_cpu(dyn_regs->gic_host_ints_irq); in gaudi2_enable_events_from_fw() local10914 WREG32(irq_handler_offset, in gaudi2_enable_events_from_fw()