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Searched refs:intel_de_write_fw (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_sprite.c97 intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), in chv_sprite_update_csc()
99 intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), in chv_sprite_update_csc()
101 intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), in chv_sprite_update_csc()
104 intel_de_write_fw(dev_priv, SPCSCC01(plane_id), in chv_sprite_update_csc()
106 intel_de_write_fw(dev_priv, SPCSCC23(plane_id), in chv_sprite_update_csc()
108 intel_de_write_fw(dev_priv, SPCSCC45(plane_id), in chv_sprite_update_csc()
110 intel_de_write_fw(dev_priv, SPCSCC67(plane_id), in chv_sprite_update_csc()
112 intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); in chv_sprite_update_csc()
114 intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), in chv_sprite_update_csc()
116 intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), in chv_sprite_update_csc()
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H A Dskl_universal_plane.c563 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc()
565 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc()
567 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc()
569 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc()
571 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc()
573 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), in icl_program_input_csc()
576 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), in icl_program_input_csc()
578 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), in icl_program_input_csc()
580 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), in icl_program_input_csc()
582 intel_de_write_fw(dev_priv, in icl_program_input_csc()
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H A Dintel_gmbus.c381 intel_de_write_fw(i915, GMBUS4(i915), irq_en); in gmbus_wait()
390 intel_de_write_fw(i915, GMBUS4(i915), 0); in gmbus_wait()
412 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); in gmbus_wait_idle()
416 intel_de_write_fw(i915, GMBUS4(i915), 0); in gmbus_wait_idle()
447 intel_de_write_fw(i915, GMBUS0(i915), in gmbus_xfer_read_chunk()
451 intel_de_write_fw(i915, GMBUS1(i915), in gmbus_xfer_read_chunk()
472 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); in gmbus_xfer_read_chunk()
529 intel_de_write_fw(i915, GMBUS3(i915), val); in gmbus_xfer_write_chunk()
530 intel_de_write_fw(i915, GMBUS1(i915), in gmbus_xfer_write_chunk()
540 intel_de_write_fw(i915, GMBUS3(i915), val); in gmbus_xfer_write_chunk()
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H A Dskl_scaler.c660 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), in glk_program_nearest_filter_coefs()
673 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set), in glk_program_nearest_filter_coefs()
677 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); in glk_program_nearest_filter_coefs()
750 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); in skl_pfit_enable()
752 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), in skl_pfit_enable()
754 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), in skl_pfit_enable()
756 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), in skl_pfit_enable()
758 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), in skl_pfit_enable()
813 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); in skl_program_plane_scaler()
814 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), in skl_program_plane_scaler()
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H A Dintel_color.c208 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]); in ilk_update_pipe_csc()
209 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]); in ilk_update_pipe_csc()
210 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]); in ilk_update_pipe_csc()
212 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
214 intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), in ilk_update_pipe_csc()
217 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
219 intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), in ilk_update_pipe_csc()
222 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
224 intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), in ilk_update_pipe_csc()
230 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe), csc->postoff[0]); in ilk_update_pipe_csc()
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H A Di9xx_plane.c424 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), in i9xx_plane_update_noarm()
438 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), in i9xx_plane_update_noarm()
440 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), in i9xx_plane_update_noarm()
470 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), in i9xx_plane_update_arm()
472 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), in i9xx_plane_update_arm()
474 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); in i9xx_plane_update_arm()
478 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), in i9xx_plane_update_arm()
481 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), in i9xx_plane_update_arm()
483 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), in i9xx_plane_update_arm()
492 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_update_arm()
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H A Dintel_cursor.c283 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_cursor_update_arm()
284 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_cursor_update_arm()
285 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); in i845_cursor_update_arm()
286 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
287 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); in i845_cursor_update_arm()
293 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
543 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), in i9xx_cursor_update_arm()
545 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); in i9xx_cursor_update_arm()
546 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); in i9xx_cursor_update_arm()
547 intel_de_write_fw(dev_priv, CURBASE(pipe), base); in i9xx_cursor_update_arm()
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H A Dintel_de.h108 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) in intel_de_write_fw() function
H A Dintel_psr.c1804 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); in intel_psr2_disable_plane_sel_fetch_arm()
1818 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_arm()
1821 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_arm()
1846 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch_noarm()
1861 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_noarm()
1867 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch_noarm()
H A Dintel_fbc.c327 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i8xx_fbc_nuke()
362 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_nuke()
H A Dintel_display.c811 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | in ilk_pfit_enable()
814 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | in ilk_pfit_enable()
816 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), in ilk_pfit_enable()
818 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), in ilk_pfit_enable()
1645 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); in ilk_pfit_disable()
1646 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); in ilk_pfit_disable()
1647 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); in ilk_pfit_disable()
H A Dintel_dmc.c563 intel_de_write_fw(i915, in intel_dmc_load_program()
H A Dskl_watermark.c2356 intel_de_write_fw(i915, reg, in skl_ddb_entry_write()
2360 intel_de_write_fw(i915, reg, 0); in skl_ddb_entry_write()
2376 intel_de_write_fw(i915, reg, val); in skl_write_wm_level()