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Searched refs:int_sel (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/arch-braswell/
H A Dgpio.h179 gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\ argument
182 .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
190 .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
/openbmc/linux/drivers/mfd/
H A Dezx-pcap.c180 u32 msr, isr, int_sel, service; in pcap_isr_work() local
189 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); in pcap_isr_work()
190 isr &= ~int_sel; in pcap_isr_work()
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_vi.h475 enum RELEASE_MEM_int_sel_enum int_sel:3; member
H A Dkfd_pm4_headers_ai.h539 enum mec_release_mem_int_sel_enum int_sel:3; member
H A Dkfd_packet_manager_vi.c289 packet->bitfields3.int_sel = in pm_release_mem_vi()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2119 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_gfx() local
2142 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2163 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_compute() local
2171 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
H A Dgfx_v8_0.c6155 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_gfx() local
6182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6250 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_compute() local
6259 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
H A Dgfx_v6_0.c1808 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v6_0_ring_emit_fence() local
1827 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
H A Dgfx_v9_4_3.c2546 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_4_3_ring_emit_fence() local
2559 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_4_3_ring_emit_fence()
H A Dgfx_v11_0.c5362 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v11_0_ring_emit_fence() local
5378 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
H A Dgfx_v9_0.c5295 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_0_ring_emit_fence() local
5315 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
H A Dgfx_v10_0.c8367 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v10_0_ring_emit_fence() local
8379 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v10_0_ring_emit_fence()