Searched refs:int_sel (Results 1 – 12 of 12) sorted by relevance
/openbmc/u-boot/arch/x86/include/asm/arch-braswell/ |
H A D | gpio.h | 179 gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\ argument 182 .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \ 190 .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
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/openbmc/linux/drivers/mfd/ |
H A D | ezx-pcap.c | 180 u32 msr, isr, int_sel, service; in pcap_isr_work() local 189 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); in pcap_isr_work() 190 isr &= ~int_sel; in pcap_isr_work()
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/openbmc/linux/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_pm4_headers_vi.h | 475 enum RELEASE_MEM_int_sel_enum int_sel:3; member
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H A D | kfd_pm4_headers_ai.h | 539 enum mec_release_mem_int_sel_enum int_sel:3; member
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H A D | kfd_packet_manager_vi.c | 289 packet->bitfields3.int_sel = in pm_release_mem_vi()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v7_0.c | 2119 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_gfx() local 2142 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx() 2163 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_compute() local 2171 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
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H A D | gfx_v8_0.c | 6155 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_gfx() local 6182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx() 6250 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_compute() local 6259 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
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H A D | gfx_v6_0.c | 1808 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v6_0_ring_emit_fence() local 1827 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
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H A D | gfx_v9_4_3.c | 2546 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_4_3_ring_emit_fence() local 2559 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_4_3_ring_emit_fence()
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H A D | gfx_v11_0.c | 5362 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v11_0_ring_emit_fence() local 5378 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
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H A D | gfx_v9_0.c | 5295 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_0_ring_emit_fence() local 5315 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
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H A D | gfx_v10_0.c | 8367 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v10_0_ring_emit_fence() local 8379 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v10_0_ring_emit_fence()
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