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Searched refs:inh_avail_mask (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcsr.c872 uint64_t inh_avail_mask; in write_mcyclecfg() local
878 inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH; in write_mcyclecfg()
879 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH : 0; in write_mcyclecfg()
880 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH : 0; in write_mcyclecfg()
881 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
883 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
885 env->mcyclecfg = val & inh_avail_mask; in write_mcyclecfg()
901 target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK | in write_mcyclecfgh() local
905 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0; in write_mcyclecfgh()
906 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0; in write_mcyclecfgh()
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