Home
last modified time | relevance | path

Searched refs:imm5 (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dxthead.decode20 %imm5 20:s5
32 &th_meminc rd rs1 imm5 imm2
44 @th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c79 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rvc_branch_rela() local
84 imm8 | imm7_6 | imm5 | imm4_3 | imm2_1; in apply_r_riscv_rvc_branch_rela()
97 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rvc_jump_rela() local
102 imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1; in apply_r_riscv_rvc_jump_rela()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc555 * Load with memop from indexed address and add (imm5 << imm2) to rs1.
557 * If preinc, then the load address is rs1 + (imm5) << imm2).
566 int imm = a->imm5 << a->imm2;
579 * Store with memop to indexed address and add (imm5 << imm2) to rs1.
581 * If preinc, then the store address is rs1 + (imm5) << imm2).
586 int imm = a->imm5 << a->imm2;
/openbmc/linux/arch/arm/probes/kprobes/
H A Dactions-thumb.c372 long imm5 = insn & 0xf8; in t16_simulate_cbz() local
374 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2); in t16_simulate_cbz()