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Searched refs:imm2 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h250 .macro VGBM vr imm2
253 .word \imm2
327 .macro VLEIx vr1, imm2, m3, opc
330 .word \imm2
333 .macro VLEIB vr1, imm2, index
334 VLEIx \vr1, \imm2, \index, 0x40
336 .macro VLEIH vr1, imm2, index
337 VLEIx \vr1, \imm2, \index, 0x41
339 .macro VLEIF vr1, imm2, index
340 VLEIx \vr1, \imm2, \index, 0x43
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsm3-ce-core.S28 .macro sm3tt1a, rd, rn, rm, imm2 argument
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
32 .macro sm3tt1b, rd, rn, rm, imm2 argument
33 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
36 .macro sm3tt2a, rd, rn, rm, imm2 argument
37 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
40 .macro sm3tt2b, rd, rn, rm, imm2 argument
41 .inst 0xce408c00 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dmacros.h157 #define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \ argument
162 insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
165 #define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \ argument
170 insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
182 #define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\ argument
186 insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
197 #define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \ argument
201 insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2; \
H A Dtest_insert.S5 # insn num result rs1 imm1 rs2 imm2
9 # insn num result rs1 imm1 imm2 imm3
H A Dtest_imask.S6 # insn num res[63:32] | imm1 rs1 imm2
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc87 * If !zext_offs, then the address is rs1 + (rs2 << imm2).
88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
91 int imm2, bool zext_offs)
98 tcg_gen_shli_tl(offs, offs, imm2);
100 tcg_gen_shli_tl(offs, src2, imm2);
343 * If !zext_offs, then address is rs1 + (rs2 << imm2).
344 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
350 TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
363 * If !zext_offs, then address is rs1 + (rs2 << imm2).
364 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
[all …]
/openbmc/qemu/target/riscv/
H A Dxthead.decode23 %imm2 25:2
31 &th_memidx rd rs1 rs2 imm2
32 &th_meminc rd rs1 imm5 imm2
43 @th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2
44 @th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
168 ((imm2) << 1))
169 #define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ argument
174 ((imm2) << 6) + \
/openbmc/qemu/target/loongarch/
H A Dinsns.decode518 &vr_ii vd rj imm imm2
552 @vr_i8i1 .... ........ . imm2:1 ........ rj:5 vd:5 &vr_ii imm=%i8s3
553 @vr_i8i2 .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s2
554 @vr_i8i3 .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s1
555 @vr_i8i4 .... ...... imm2:4 imm:s8 rj:5 vd:5 &vr_ii
556 @vr_i8i2x .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s3
557 @vr_i8i3x .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s2
558 @vr_i8i4x .... ...... imm2:4 ........ rj:5 vd:5 &vr_ii imm=%i8s1
559 @vr_i8i5x .... ..... imm2:5 imm:s8 rj:5 vd:5 &vr_ii
H A Ddisas.c850 output(ctx, mnemonic, "v%d, r%d, 0x%x, 0x%x", a->vd, a->rj, a->imm, a->imm2); in output_vr_ii()
1775 output(ctx, mnemonic, "x%d, r%d, 0x%x, 0x%x", a->vd, a->rj, a->imm, a->imm2); in output_vr_ii_x()
/openbmc/qemu/target/arm/tcg/
H A Dcrypto_helper.c550 uint32_t imm2 = simd_data(desc); in crypto_sm3tt() local
553 assert(imm2 < 4); in crypto_sm3tt()
568 t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2); in crypto_sm3tt()
H A Da64.decode696 ### Cryptographic three-register, imm2
H A Dsve.decode441 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
H A Dtranslate-sve.c1125 tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2))
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c31 u32 imm2; /* 2nd value in predicate condition, left-to-right */ member
64 return ((args->val1 & args->imm1) != args->imm2); in pand_neq()
69 return (((args->val1 & args->imm1) != args->imm2) && in pand_neq_x2()
75 return ((args->val1 != args->imm1) && (idle_chk_errors > args->imm2)); in pneq_err()
100 return (((args->val1 >> args->imm1) & args->imm2) != args->imm3); in prsh_and_neq()
105 return ((args->val1 == args->imm1) && (args->val2 != args->imm2)); in peq_neq_r2()
110 return ((args->val1 == args->imm1) && (args->val2 != args->imm2) && in peq_neq_neq_r2()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc5414 tcg_gen_ld_i64(val, tcg_env, vec_reg_offset(a->vd, a->imm2, mop));