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Searched refs:imm12 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h155 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \ argument
156 aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
159 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD) argument
160 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB) argument
161 #define A64_ADDS_I(sf, Rd, Rn, imm12) \ argument
162 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
163 #define A64_SUBS_I(sf, Rd, Rn, imm12) \ argument
164 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
166 #define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12) argument
168 #define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12) argument
/openbmc/linux/arch/arm/kernel/
H A Dphys2virt.S158 @ rotation value. (The effective value of the immediate is imm12<7:0>
159 @ rotated right by [2 * imm12<11:8>] bits)
163 @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 |
164 @ SUB | cond | 0 0 1 0 0 1 0 0 | Rn | Rd | imm12 |
165 @ MOV | cond | 0 0 1 1 1 0 1 0 | Rn | Rd | imm12 |
166 @ MVN | cond | 0 0 1 1 1 1 1 0 | Rn | Rd | imm12 |
179 @ MOVW | cond | 0 0 1 1 0 0 0 0 | imm4 | Rd | imm12 |
194 bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction
/openbmc/qemu/hw/mips/
H A Dbootloader.c165 static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) in bl_gen_ori_nm() argument
169 assert(extract32(imm12, 0, 12) == imm12); in bl_gen_ori_nm()
173 insn = deposit32(insn, 0, 12, imm12); in bl_gen_ori_nm()
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc316 int imm12 = encode_imm(offset);
318 if (imm12 >= 0) {
319 *src_rw = deposit32(*src_rw, 0, 12, imm12);
364 * Return < 0 if @imm cannot be encoded, else the entire imm12 field.
626 TCGReg rt, TCGReg rn, int imm12, bool p, bool w)
629 if (imm12 < 0) {
630 imm12 = -imm12;
634 (rn << 16) | (rt << 12) | imm12);
638 TCGReg rn, int imm12)
640 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
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/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.c311 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12) in arm_bpf_ldst_imm12() argument
314 if (imm12 >= 0) in arm_bpf_ldst_imm12()
317 imm12 = -imm12; in arm_bpf_ldst_imm12()
318 return op | (imm12 & ARM_INST_LDST__IMM12); in arm_bpf_ldst_imm12()
439 int imm12 = imm8m(val); in emit_mov_i() local
441 if (imm12 >= 0) in emit_mov_i()
442 emit(ARM_MOV_I(rd, imm12), ctx); in emit_mov_i()
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c51 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela() local
56 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc788 intptr_t imm12 = sextreg(offset, 0, 12);
790 if (offset != imm12) {
794 imm12 = sextreg(diff, 0, 12);
795 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12);
797 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
817 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
823 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12));
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc944 intptr_t imm12 = sextreg(offset, 0, 12);
946 if (offset != imm12) {
950 imm12 = sextreg(diff, 0, 12);
951 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
953 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
966 tcg_out_opc_store(s, opc, addr, data, imm12);
975 tcg_out_opc_imm(s, opc, data, addr, imm12);
/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h252 u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4); in rv_b_insn() local
255 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn()
/openbmc/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc2096 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc2211 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc2597 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc2865 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc2965 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc2784 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc4324 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc10747 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc12464 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc43701 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },