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Searched refs:idle_loop1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c203 .idle_loop1 = RW_MGR_IDLE_LOOP1,
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h137 u8 idle_loop1; member
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c810 writel(rwcfg->idle_loop1, in delay_for_n_mem_clocks()
813 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()