Searched refs:hdmi_clk_cfg (Results 1 – 6 of 6) sorted by relevance
101 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_hdmi_hpd_detect()111 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()139 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_shutdown()227 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()265 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
349 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_dw_hdmi_probe()359 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_dw_hdmi_probe()
79 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ member
84 u32 hdmi_clk_cfg; /* 0x150 */ member
196 u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ member
101 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ member