Home
last modified time | relevance | path

Searched refs:h_sync_width (Results 1 – 25 of 32) sorted by relevance

12

/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx.h43 u16 h_sync_width; member
H A Dlogicore_dp_tx.c139 u16 h_sync_width; member
2086 set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width); in set_msa_values()
2131 dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width; in logicore_dp_tx_set_msa()
2205 .h_sync_width = 96, in logicore_dp_tx_enable()
2222 .h_sync_width = 108, in logicore_dp_tx_enable()
2239 .h_sync_width = 136, in logicore_dp_tx_enable()
H A Dipu_disp.c830 uint16_t h_start_width, uint16_t h_sync_width, in ipu_init_sync_panel() argument
844 if ((v_sync_width == 0) || (h_sync_width == 0)) in ipu_init_sync_panel()
853 h_total = width + h_sync_width + h_start_width + h_end_width; in ipu_init_sync_panel()
1085 DI_SYNC_CLK, 0, h_sync_width * 2); in ipu_init_sync_panel()
1101 h_sync_width + h_start_width, DI_SYNC_CLK, in ipu_init_sync_panel()
H A Dipu.h232 uint16_t h_start_width, uint16_t h_sync_width,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c350 hw_crtc_timing.h_sync_width; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
353 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
421 MSA_DATA_LANE_0, hsp | (hw_crtc_timing.h_sync_width >> 8), in dcn31_hpo_dp_stream_enc_set_stream_attribute()
427 MSA_DATA_LANE_0, hw_crtc_timing.h_sync_width & 0xff, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp_info.h28 unsigned int h_sync_width; member
/openbmc/linux/drivers/video/fbdev/
H A Dacornfb.h59 u_int h_sync_width; member
H A Dacornfb.c122 vidc.h_sync_width = var->hsync_len - 8; in acornfb_set_timing()
123 vidc.h_border_start = vidc.h_sync_width + var->left_margin + 8 - 12; in acornfb_set_timing()
164 vidc_writel(0x81000000 | vidc.h_sync_width); in acornfb_set_timing()
226 printk(KERN_DEBUG " H-sync-width : %d\n", vidc.h_sync_width); in acornfb_set_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c112 if (timing->h_sync_width < optc1->min_h_sync_width || in optc201_validate_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h177 uint32_t h_sync_width; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c466 hw_crtc_timing.h_sync_width; in dce110_stream_encoder_dp_set_stream_attribute()
469 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dce110_stream_encoder_dp_set_stream_attribute()
486 hw_crtc_timing.h_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c431 hw_crtc_timing.h_sync_width; in enc1_stream_encoder_dp_set_stream_attribute()
434 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in enc1_stream_encoder_dp_set_stream_attribute()
449 hw_crtc_timing.h_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
H A Ddcn10_optc.c193 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); in optc1_program_timing()
628 if (timing->h_sync_width < optc1->min_h_sync_width || in optc1_validate_timing()
1315 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; in optc1_get_hw_timing()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp.c31 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + in exynos_dp_disp_info()
893 priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
H A Dexynos_dp_lowlevel.c1094 writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width), in exynos_dp_config_video_bist()
1096 writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width), in exynos_dp_config_video_bist()
/openbmc/linux/drivers/gpu/drm/tegra/
H A Dhdmi.c1207 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; in tegra_hdmi_encoder_enable() local
1233 h_sync_width = mode->hsync_end - mode->hsync_start; in tegra_hdmi_encoder_enable()
1262 pulse_start = 1 + h_sync_width + h_back_porch - 10; in tegra_hdmi_encoder_enable()
1314 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + in tegra_hdmi_encoder_enable()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_sdvo_regs.h78 u8 h_sync_width; /**< lower 8 bits (pixels) */ member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c265 (timing->h_sync_width % 2 == 0); in is_h_timing_divisible_by_2()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_sdvo_regs.h89 u8 h_sync_width; /* lower 8 bits (pixels) */ member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c316 bp_params.h_sync_width = patched_crtc_timing.h_sync_width; in dce110_timing_generator_program_timing_generator()
1161 timing->h_sync_width); in dce110_timing_generator_validate_timing()
H A Ddce110_timing_generator_v.c325 timing->h_sync_width, in dce110_timing_generator_v_program_blanking()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h884 uint32_t h_sync_width; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table2.c593 params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
H A Dcommand_table.c1838 params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width)); in set_crtc_timing_v1()
1923 params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()

12