| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v2_1.c | 144 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
149 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_1_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_1_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
167 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
236 if (adev->gmc.translate_further) { in gfxhub_v2_1_init_cache_regs()
323 !adev->gmc.noretry); in gfxhub_v2_1_setup_vmid_config()
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| H A D | amdgpu_gmc.c | 52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
85 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
89 amdgpu_bo_unref(&adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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| H A D | gmc_v9_0.c | 734 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
735 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
738 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_set_irq_funcs()
739 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
740 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
824 if (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb()
859 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
927 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
969 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb_pasid()
1160 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
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| H A D | gmc_v10_0.c | 190 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
191 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
194 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
195 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
248 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
306 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
597 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
677 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
678 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
742 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
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| H A D | gmc_v11_0.c | 155 adev->gmc.vm_fault.num_types = 1; in gmc_v11_0_set_irq_funcs()
156 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; in gmc_v11_0_set_irq_funcs()
159 adev->gmc.ecc_irq.num_types = 1; in gmc_v11_0_set_irq_funcs()
160 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; in gmc_v11_0_set_irq_funcs()
209 spin_lock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_vm_hub()
267 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_vm_hub()
502 adev->gmc.vram_start; in gmc_v11_0_get_vm_pde()
505 if (!adev->gmc.translate_further) in gmc_v11_0_get_vm_pde()
585 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; in gmc_v11_0_set_gmc_funcs()
648 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v11_0_early_init()
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| H A D | gmc_v7_0.c | 158 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v7_0_init_microcode()
161 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
182 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
185 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
188 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
191 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
285 adev->gmc.vram_start >> 12); in gmc_v7_0_mc_program()
287 adev->gmc.vram_end >> 12); in gmc_v7_0_mc_program()
319 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); in gmc_v7_0_mc_init()
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| H A D | gmc_v8_0.c | 259 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v8_0_init_microcode()
262 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
291 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
294 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
297 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
300 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
303 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
360 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
363 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
366 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
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| H A D | gmc_v6_0.c | 135 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v6_0_init_microcode()
140 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_init_microcode()
153 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
250 adev->gmc.vram_start >> 12); in gmc_v6_0_mc_program()
252 adev->gmc.vram_end >> 12); in gmc_v6_0_mc_program()
309 adev->gmc.vram_width = numchan * chansize; in gmc_v6_0_mc_init()
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| H A D | gfxhub_v1_0.c | 58 if (adev->gmc.pdb0_bo) in gfxhub_v1_0_init_gart_aperture_regs()
59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_0_init_gart_aperture_regs()
68 if (adev->gmc.pdb0_bo) { in gfxhub_v1_0_init_gart_aperture_regs()
70 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
72 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
85 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
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| H A D | amdgpu_xgmi.c | 324 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
485 if (!adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
496 if (hive->hive_id == adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
548 hive->hive_id = adev->gmc.xgmi.hive_id; in amdgpu_get_xgmi_hive()
619 request_adev->gmc.xgmi.node_id, in amdgpu_xgmi_set_pstate()
620 request_adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_set_pstate()
651 adev->gmc.xgmi.node_id, in amdgpu_xgmi_update_topology()
652 adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_update_topology()
672 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) in amdgpu_xgmi_get_hops_count()
684 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) in amdgpu_xgmi_get_num_links()
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| H A D | gfxhub_v1_2.c | 80 if (adev->gmc.pdb0_bo) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
81 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
91 if (adev->gmc.pdb0_bo) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
94 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
101 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
108 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
111 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
115 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
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| H A D | gfxhub_v1_1.c | 88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
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| H A D | amdgpu_gmc.h | 338 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((ad…
340 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
342 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((…
343 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(…
344 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
345 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (l…
346 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapp…
348 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
350 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
360 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) in amdgpu_gmc_vram_full_visible() argument
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| H A D | mmhub_v1_8.c | 48 adev->gmc.fb_start = base; in mmhub_v1_8_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_8_get_fb_location()
82 if (adev->gmc.pdb0_bo) in mmhub_v1_8_init_gart_aperture_regs()
83 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_8_init_gart_aperture_regs()
94 if (adev->gmc.pdb0_bo) { in mmhub_v1_8_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
100 (u32)(adev->gmc.fb_start >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
107 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
112 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
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| H A D | aqua_vanjaram.c | 416 if (adev->gmc.num_mem_partitions == 1) in __aqua_vanjaram_get_auto_mode()
419 if (adev->gmc.num_mem_partitions == num_xcc) in __aqua_vanjaram_get_auto_mode()
422 if (adev->gmc.num_mem_partitions == num_xcc / 2) in __aqua_vanjaram_get_auto_mode()
426 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) in __aqua_vanjaram_get_auto_mode()
441 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; in __aqua_vanjaram_is_valid_mode()
443 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; in __aqua_vanjaram_is_valid_mode()
445 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
446 adev->gmc.num_mem_partitions == 3) && in __aqua_vanjaram_is_valid_mode()
450 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
451 adev->gmc.num_mem_partitions == 4) && in __aqua_vanjaram_is_valid_mode()
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| H A D | mmhub_v1_0.c | 48 adev->gmc.fb_start = base; in mmhub_v1_0_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_0_get_fb_location()
75 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_0_init_gart_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v1_0_init_system_aperture_regs()
109 max((adev->gmc.fb_end >> 18) + 0x1, in mmhub_v1_0_init_system_aperture_regs()
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| H A D | gfxhub_v3_0.c | 140 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_init_system_aperture_regs()
167 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v3_0_init_system_aperture_regs()
235 if (adev->gmc.translate_further) { in gfxhub_v3_0_init_cache_regs()
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| H A D | amdgpu_amdkfd.c | 201 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_init()
212 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; in amdgpu_amdkfd_device_fini_sw()
427 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
434 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
435 mem_info->local_mem_size_private = adev->gmc.real_vram_size - in amdgpu_amdkfd_get_local_mem_info()
436 adev->gmc.visible_vram_size; in amdgpu_amdkfd_get_local_mem_info()
438 mem_info->vram_width = adev->gmc.vram_width; in amdgpu_amdkfd_get_local_mem_info()
441 &adev->gmc.aper_base, in amdgpu_amdkfd_get_local_mem_info()
535 adev->gmc.xgmi.physical_node_id, in amdgpu_amdkfd_get_xgmi_hops_count()
536 peer_adev->gmc.xgmi.physical_node_id, ret); in amdgpu_amdkfd_get_xgmi_hops_count()
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| H A D | gfxhub_v2_0.c | 141 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
143 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_0_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_0_init_gart_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_0_init_system_aperture_regs()
233 if (adev->gmc.translate_further) { in gfxhub_v2_0_init_cache_regs()
314 !adev->gmc.noretry); in gfxhub_v2_0_setup_vmid_config()
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| H A D | gfxhub_v3_0_3.c | 143 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
148 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v3_0_3_init_gart_aperture_regs()
150 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v3_0_3_init_gart_aperture_regs()
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_3_init_system_aperture_regs()
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
169 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v3_0_3_init_system_aperture_regs()
172 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start in gfxhub_v3_0_3_init_system_aperture_regs()
240 if (adev->gmc.translate_further) { in gfxhub_v3_0_3_init_cache_regs()
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| H A D | mmhub_v2_3.c | 140 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
142 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
145 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v2_3_init_gart_aperture_regs()
147 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v2_3_init_gart_aperture_regs()
157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_3_init_system_aperture_regs()
158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_3_init_system_aperture_regs()
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v2_3_init_system_aperture_regs()
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v2_3_init_system_aperture_regs()
228 if (adev->gmc.translate_further) { in mmhub_v2_3_init_cache_regs()
313 !adev->gmc.noretry); in mmhub_v2_3_setup_vmid_config()
[all …]
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| H A D | mmhub_v3_0_2.c | 150 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
152 (u32)(adev->gmc.gart_start >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
155 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v3_0_2_init_gart_aperture_regs()
157 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v3_0_2_init_gart_aperture_regs()
167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v3_0_2_init_system_aperture_regs()
178 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
180 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in mmhub_v3_0_2_init_system_aperture_regs()
184 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + in mmhub_v3_0_2_init_system_aperture_regs()
253 if (adev->gmc.translate_further) { in mmhub_v3_0_2_init_cache_regs()
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| H A D | amdgpu_ttm.c | 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && in amdgpu_evict_flags()
150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; in amdgpu_evict_flags()
223 *addr = adev->gmc.gart_start; in amdgpu_ttm_map_buffer()
435 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) in amdgpu_res_cpu_visible()
600 mem->bus.offset += adev->gmc.aper_base; in amdgpu_ttm_io_mem_reserve()
627 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; in amdgpu_ttm_io_mem_pfn()
643 return adev->gmc.gart_start; in amdgpu_ttm_domain_start()
645 return adev->gmc.vram_start; in amdgpu_ttm_domain_start()
992 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; in amdgpu_ttm_alloc_gart()
1098 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) in amdgpu_ttm_tt_create()
[all …]
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| H A D | amdgpu_object.c | 134 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; in amdgpu_bo_placement_from_domain()
137 if (adev->gmc.mem_partitions && mem_id >= 0) { in amdgpu_bo_placement_from_domain()
138 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; in amdgpu_bo_placement_from_domain()
143 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; in amdgpu_bo_placement_from_domain()
596 if (adev->gmc.mem_partitions) in amdgpu_bo_create()
629 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && in amdgpu_bo_create()
1072 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { in amdgpu_bo_init()
1074 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, in amdgpu_bo_init()
1075 adev->gmc.aper_size); in amdgpu_bo_init()
1083 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, in amdgpu_bo_init()
[all …]
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| /openbmc/linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_gfxpll.c | 82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
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