Searched refs:gfxclk (Results 1 – 19 of 19) sorted by relevance
101 static int gfxclk; /* force FBI freq in Mhz . Dangerous */ variable1194 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) { in sst_init()1195 printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk); in sst_init()1196 gfx_clock = gfxclk *1000; in sst_init()1197 } else if (gfxclk) { in sst_init()1198 printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk); in sst_init()1303 gfxclk = simple_strtoul (this_opt+7, NULL, 0); in sstfb_setup()1532 module_param(gfxclk, int, 0);1533 MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
342 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; in smu_v12_0_get_vbios_bootup_values()359 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; in smu_v12_0_get_vbios_bootup_values()
297 clock_limit = smu->smu_table.boot_values.gfxclk; in renoir_get_dpm_ultimate_freq()
123 gfxclk=x gfxclk:x Force graphic clock frequency (in MHz).
605 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; in smu_v13_0_get_vbios_bootup_values()619 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; in smu_v13_0_get_vbios_bootup_values()634 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; in smu_v13_0_get_vbios_bootup_values()1563 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v13_0_get_dpm_ultimate_freq()
740 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v13_0_5_get_dpm_ultimate_freq()
765 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v13_0_4_get_dpm_ultimate_freq()
874 clock_limit = smu->smu_table.boot_values.gfxclk; in yellow_carp_get_dpm_ultimate_freq()
345 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in aldebaran_set_default_dpm_table()
612 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_7_set_default_dpm_table()
622 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_0_set_default_dpm_table()
554 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; in smu_v11_0_get_vbios_bootup_values()571 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; in smu_v11_0_get_vbios_bootup_values()1713 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v11_0_get_dpm_ultimate_freq()
943 clock_limit = smu->smu_table.boot_values.gfxclk; in vangogh_get_dpm_ultimate_freq()
364 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in arcturus_set_default_dpm_table()
1006 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in navi10_set_default_dpm_table()
973 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in sienna_cichlid_set_default_dpm_table()
283 uint32_t gfxclk; member
524 uint32_t gfxclk; member
837 limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit); in get_hard_limits()