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Searched refs:gfx9 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c325 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp3_program_tiling()
326 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp3_program_tiling()
327 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), in hubp3_program_tiling()
328 NUM_PKRS, log_2(info->gfx9.num_pkrs)); in hubp3_program_tiling()
331 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
332 META_LINEAR, info->gfx9.meta_linear, in hubp3_program_tiling()
333 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp3_program_tiling()
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c217 tiling_info->gfx9.num_pipes = in fill_gfx9_tiling_info_from_device()
219 tiling_info->gfx9.num_banks = in fill_gfx9_tiling_info_from_device()
221 tiling_info->gfx9.pipe_interleave = in fill_gfx9_tiling_info_from_device()
223 tiling_info->gfx9.num_shader_engines = in fill_gfx9_tiling_info_from_device()
225 tiling_info->gfx9.max_compressed_frags = in fill_gfx9_tiling_info_from_device()
227 tiling_info->gfx9.num_rb_per_se = in fill_gfx9_tiling_info_from_device()
229 tiling_info->gfx9.shaderEnable = 1; in fill_gfx9_tiling_info_from_device()
231 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in fill_gfx9_tiling_info_from_device()
250 tiling_info->gfx9.num_pipes = 1u << pipes_log2; in fill_gfx9_tiling_info_from_modifier()
251 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); in fill_gfx9_tiling_info_from_modifier()
[all …]
H A Damdgpu_dm_trace.h450 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
H A Damdgpu_dm.c6575 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c149 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp1_program_tiling()
150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp1_program_tiling()
152 NUM_SE, log_2(info->gfx9.num_shader_engines), in hubp1_program_tiling()
153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), in hubp1_program_tiling()
154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp1_program_tiling()
157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
158 META_LINEAR, info->gfx9.meta_linear, in hubp1_program_tiling()
159 RB_ALIGNED, info->gfx9.rb_aligned, in hubp1_program_tiling()
160 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp1_program_tiling()
H A Ddcn10_resource.c1230 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c437 GRPH_SW_MODE, info->gfx9.swizzle, in program_tiling()
438 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), in program_tiling()
439 GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), in program_tiling()
440 GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), in program_tiling()
442 GRPH_SE_ENABLE, info->gfx9.shaderEnable); in program_tiling()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c170 plane_state->tiling_info.gfx9.swizzle); in pre_surface_trace()
256 update->plane_info->tiling_info.gfx9.swizzle); in update_surface_trace()
H A Ddc_hw_sequencer.c842 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
H A Ddc_resource.c3133 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
H A Ddc.c2440 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c315 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp2_program_tiling()
316 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp2_program_tiling()
317 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp2_program_tiling()
320 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
H A Ddcn20_resource.c2208 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S; in dcn20_patch_unknown_plane_state()
2210 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D; in dcn20_patch_unknown_plane_state()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h402 } gfx9; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c374 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1010 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1678 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
1679 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()