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Searched refs:gb_addr_config (Results 1 – 25 of 43) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c347 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
349 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
351 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
353 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
355 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
357 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
359 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
361 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
363 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
365 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
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H A Dgfx_v6_0.c1564 u32 gb_addr_config = 0; in gfx_v6_0_constants_init() local
1586 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1603 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1620 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1637 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1654 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1680 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v6_0_constants_init()
1684 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1687 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1690 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
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H A Damdgpu_gfx.h177 struct gb_addr_config { struct
212 unsigned gb_addr_config; member
220 struct gb_addr_config gb_addr_config_fields;
H A Duvd_v3_1.c270 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
271 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
272 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
H A Duvd_v4_2.c599 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
600 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
601 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
H A Duvd_v5_0.c303 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
304 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
305 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
H A Djpeg_v3_0.c350 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
352 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
H A Dgfx_v9_0.c1840 u32 gb_addr_config; in gfx_v9_0_gpu_early_init() local
1850 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
1858 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
1868 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
1869 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
1870 gb_addr_config |= 0x22014042; in gfx_v9_0_gpu_early_init()
1884 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
1886 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; in gfx_v9_0_gpu_early_init()
1895 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
1896 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
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H A Dgfx_v7_0.c1893 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1894 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1895 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
4210 u32 gb_addr_config; in gfx_v7_0_gpu_early_init() local
4231 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4248 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4265 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4284 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4336 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v7_0_gpu_early_init()
4340 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); in gfx_v7_0_gpu_early_init()
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H A Dgfx_v8_0.c1654 u32 gb_addr_config; in gfx_v8_0_gpu_early_init() local
1676 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1693 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1708 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1723 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1740 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1757 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1774 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1791 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1846 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
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H A Djpeg_v2_5.c343 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start()
345 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start()
H A Dvcn_v4_0_3.c519 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
521 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1139 adev->gfx.config.gb_addr_config); in vcn_v4_0_3_start()
1141 adev->gfx.config.gb_addr_config); in vcn_v4_0_3_start()
H A Dsoc21.c295 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
296 return adev->gfx.config.gb_addr_config; in soc21_get_register_value()
H A Dgfx_v9_4_3.c680 u32 gb_addr_config; in gfx_v9_4_3_gpu_early_init() local
692 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); in gfx_v9_4_3_gpu_early_init()
699 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_4_3_gpu_early_init()
703 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
712 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
717 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
722 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
727 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
732 adev->gfx.config.gb_addr_config, in gfx_v9_4_3_gpu_early_init()
H A Duvd_v6_0.c627 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
628 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
629 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
H A Dgfx_v11_0.c4215 u32 gb_addr_config; in get_gb_addr_config() local
4217 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4218 if (gb_addr_config == 0) in get_gb_addr_config()
4222 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); in get_gb_addr_config()
4224 adev->gfx.config.gb_addr_config = gb_addr_config; in get_gb_addr_config()
4227 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4234 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4237 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4240 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4243 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
H A Duvd_v7_0.c718 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
720 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
722 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
H A Djpeg_v4_0_3.c497 adev->gfx.config.gb_addr_config); in jpeg_v4_0_3_start()
499 adev->gfx.config.gb_addr_config); in jpeg_v4_0_3_start()
H A Dvcn_v2_5.c562 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1050 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
1052 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dni.c880 u32 gb_addr_config = 0; in cayman_gpu_init() local
913 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
987 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1018 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; in cayman_gpu_init()
1020 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; in cayman_gpu_init()
1022 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; in cayman_gpu_init()
1024 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; in cayman_gpu_init()
1026 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; in cayman_gpu_init()
1028 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; in cayman_gpu_init()
1074 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cayman_gpu_init()
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H A Devergreen.c3137 u32 gb_addr_config; in evergreen_gpu_init() local
3178 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3200 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3222 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3245 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3267 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3295 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3317 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3339 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3361 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
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H A Dsi.c3090 u32 gb_addr_config = 0; in si_gpu_init() local
3113 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3130 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3148 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3165 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3182 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3218 gb_addr_config &= ~ROW_SIZE_MASK; in si_gpu_init()
3222 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3225 gb_addr_config |= ROW_SIZE(1); in si_gpu_init()
3228 gb_addr_config |= ROW_SIZE(2); in si_gpu_init()
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H A Dcik.c3170 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init() local
3192 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3209 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3226 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3245 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3279 gb_addr_config &= ~ROW_SIZE_MASK; in cik_gpu_init()
3283 gb_addr_config |= ROW_SIZE(0); in cik_gpu_init()
3286 gb_addr_config |= ROW_SIZE(1); in cik_gpu_init()
3289 gb_addr_config |= ROW_SIZE(2); in cik_gpu_init()
3320 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cik_gpu_init()
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/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c588 u32 gb_addr_config; in add_gfx11_modifiers() local
598 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in add_gfx11_modifiers()
599 ASSERT(gb_addr_config != 0); in add_gfx11_modifiers()
601 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); in add_gfx11_modifiers()
603 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); in add_gfx11_modifiers()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dkgd_kfd_interface.h150 uint32_t gb_addr_config; member

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