Searched refs:fpdscr (Results 1 – 6 of 6) sorted by relevance
495 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()502 TCGv_i32 control, sfpa, fpscr, fpdscr; in gen_M_fp_sysreg_read() local509 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()540 fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()542 fpdscr, fpscr); in gen_M_fp_sysreg_read()
180 fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); in gen_update_fp_context()
486 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),1015 if (extract32(env->v7m.fpdscr[M_REG_NS], in cpu_post_load()1017 extract32(env->v7m.fpdscr[M_REG_S], in cpu_post_load()
407 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()408 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
566 uint32_t fpdscr[M_REG_NUM_BANKS]; member
1539 return cpu->env.v7m.fpdscr[attrs.secure]; in nvic_readl()2132 cpu->env.v7m.fpdscr[attrs.secure] = value; in nvic_writel()