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Searched refs:fpdscr (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c495 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
502 TCGv_i32 control, sfpa, fpscr, fpdscr; in gen_M_fp_sysreg_read() local
509 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
540 fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
542 fpdscr, fpscr); in gen_M_fp_sysreg_read()
H A Dtranslate-vfp.c180 fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); in gen_update_fp_context()
/openbmc/qemu/target/arm/
H A Dmachine.c486 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
1015 if (extract32(env->v7m.fpdscr[M_REG_NS], in cpu_post_load()
1017 extract32(env->v7m.fpdscr[M_REG_S], in cpu_post_load()
H A Dcpu.c407 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
408 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
H A Dcpu.h566 uint32_t fpdscr[M_REG_NUM_BANKS]; member
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1539 return cpu->env.v7m.fpdscr[attrs.secure]; in nvic_readl()
2132 cpu->env.v7m.fpdscr[attrs.secure] = value; in nvic_writel()