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Searched refs:field_val (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c114 u32 reg_val, field_val; in imx_ddr_size() local
119 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT; in imx_ddr_size()
120 bits += 2 - field_val; in imx_ddr_size()
122 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT; in imx_ddr_size()
123 if (field_val > 1) in imx_ddr_size()
124 bits += field_val - 1; in imx_ddr_size()
128 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT; in imx_ddr_size()
129 if (field_val <= 7) in imx_ddr_size()
131 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT; in imx_ddr_size()
132 if (field_val <= 7) in imx_ddr_size()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvega20_ih.c677 uint32_t data, def, field_val; in vega20_ih_update_clockgating_state() local
681 field_val = enable ? 0 : 1; in vega20_ih_update_clockgating_state()
683 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
685 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
687 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
689 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
691 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
693 DYN_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
695 REG_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
H A Dvega10_ih.c589 uint32_t data, def, field_val; in vega10_ih_update_clockgating_state() local
593 field_val = enable ? 0 : 1; in vega10_ih_update_clockgating_state()
599 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
602 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
604 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
606 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
608 DYN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
610 REG_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
H A Dnavi10_ih.c656 uint32_t data, def, field_val; in navi10_ih_update_clockgating_state() local
660 field_val = enable ? 0 : 1; in navi10_ih_update_clockgating_state()
662 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
664 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
666 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
668 DYN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
670 REG_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
H A Dih_v6_1.c633 uint32_t data, def, field_val; in ih_v6_1_update_clockgating_state() local
637 field_val = enable ? 0 : 1; in ih_v6_1_update_clockgating_state()
639 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
641 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
643 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
645 DYN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
647 REG_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
H A Dih_v6_0.c660 uint32_t data, def, field_val; in ih_v6_0_update_clockgating_state() local
664 field_val = enable ? 0 : 1; in ih_v6_0_update_clockgating_state()
666 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
668 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
670 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
672 DYN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
674 REG_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
H A Damdgpu_psp.h465 uint32_t field_val, uint32_t mask, bool check_changed);
467 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
H A Damdgpu.h1227 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
1229 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
125 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1272 u32 read_val, field_val; in cdns_torrent_dp_configure_rate() local
1279 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); in cdns_torrent_dp_configure_rate()
1282 field_val &= ~(cdns_phy->dp_pll); in cdns_torrent_dp_configure_rate()
1283 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); in cdns_torrent_dp_configure_rate()
1323 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); in cdns_torrent_dp_configure_rate()
1326 field_val |= cdns_phy->dp_pll; in cdns_torrent_dp_configure_rate()
1327 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); in cdns_torrent_dp_configure_rate()