Home
last modified time | relevance | path

Searched refs:fcsr0 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/arch/mips/kernel/
H A Dfpu-probe.c51 unsigned long sr, mask, fcsr, fcsr0, fcsr1; in cpu_set_fpu_fcsr_mask() local
59 fcsr0 = fcsr & mask; in cpu_set_fpu_fcsr_mask()
60 write_32bit_cp1_register(CP1_STATUS, fcsr0); in cpu_set_fpu_fcsr_mask()
61 fcsr0 = read_32bit_cp1_register(CP1_STATUS); in cpu_set_fpu_fcsr_mask()
71 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; in cpu_set_fpu_fcsr_mask()
84 unsigned long sr, fir, fcsr, fcsr0, fcsr1; in cpu_set_fpu_2008() local
98 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | in cpu_set_fpu_2008()
100 write_32bit_cp1_register(CP1_STATUS, fcsr0); in cpu_set_fpu_2008()
101 fcsr0 = read_32bit_cp1_register(CP1_STATUS); in cpu_set_fpu_2008()
115 if (fcsr0 & FPU_CSR_MAC2008) in cpu_set_fpu_2008()
[all …]
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmov.c.inc97 tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
99 TCGv_i32 fcsr0 = tcg_temp_new_i32();
102 tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
105 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
106 tcg_gen_or_i32(fcsr0, fcsr0, temp);
107 tcg_gen_st_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
130 tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
/openbmc/qemu/linux-user/loongarch64/
H A Dcpu_loop.c55 if (GET_FP_CAUSE(env->fcsr0) & FP_INVALID) { in cpu_loop()
57 } else if (GET_FP_CAUSE(env->fcsr0) & FP_DIV0) { in cpu_loop()
59 } else if (GET_FP_CAUSE(env->fcsr0) & FP_OVERFLOW) { in cpu_loop()
61 } else if (GET_FP_CAUSE(env->fcsr0) & FP_UNDERFLOW) { in cpu_loop()
63 } else if (GET_FP_CAUSE(env->fcsr0) & FP_INEXACT) { in cpu_loop()
H A Dsignal.c185 __put_user(env->fcsr0, &lasx_ctx->fcsr); in setup_sigframe()
200 __put_user(env->fcsr0, &lsx_ctx->fcsr); in setup_sigframe()
214 __put_user(env->fcsr0, &fpu_ctx->fcsr); in setup_sigframe()
302 __get_user(env->fcsr0, &lasx_ctx->fcsr); in restore_sigframe()
314 __get_user(env->fcsr0, &lsx_ctx->fcsr); in restore_sigframe()
325 __get_user(env->fcsr0, &fpu_ctx->fcsr); in restore_sigframe()
/openbmc/linux/arch/loongarch/include/asm/
H A Dfpregdef.h48 #define fcsr0 $r0 macro
53 #define fcsr0 $fcsr0 macro
H A Dasmmacro.h43 movfcsr2gr \tmp, fcsr0
60 movgr2fcsr fcsr0, \tmp0
H A Dloongarch.h1431 #define LOONGARCH_FCSR0 $fcsr0
/openbmc/linux/arch/loongarch/kernel/
H A Dcpu-probe.c32 unsigned long sr, mask, fcsr, fcsr0, fcsr1; in cpu_set_fpu_fcsr_mask() local
40 fcsr0 = fcsr & mask; in cpu_set_fpu_fcsr_mask()
41 write_fcsr(LOONGARCH_FCSR0, fcsr0); in cpu_set_fpu_fcsr_mask()
42 fcsr0 = read_fcsr(LOONGARCH_FCSR0); in cpu_set_fpu_fcsr_mask()
52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask; in cpu_set_fpu_fcsr_mask()
H A Dgenex.S63 movfcsr2gr a1, fcsr0
H A Dfpu.S139 movfcsr2gr \tmp0, fcsr0
152 movgr2fcsr fcsr0, \tmp0
406 movgr2fcsr fcsr0, a0
/openbmc/qemu/target/loongarch/
H A Dgdbstub.c97 return gdb_get_reg32(mem_buf, env->fcsr0); in loongarch_gdb_get_fpu()
115 env->fcsr0 = ldl_le_p(mem_buf); in loongarch_gdb_set_fpu()
H A Darch_dump.c99 note.fpu.fcsr = cpu_to_dump64(s, env->fcsr0); in loongarch_write_elf64_fprpreg()
H A Dmachine.c42 VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
H A Dcpu.c523 env->fcsr0 = 0x0; in loongarch_cpu_reset_hold()
751 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); in loongarch_cpu_dump_state()
H A Dcpu.h307 uint32_t fcsr0; member
/openbmc/qemu/target/loongarch/tcg/
H A Dfpu_helper.c31 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in restore_fp_status()
67 SET_FP_CAUSE(env->fcsr0, flags); in update_fcsr0_mask()
71 SET_FP_CAUSE(env->fcsr0, flags); in update_fcsr0_mask()
74 if (GET_FP_ENABLES(env->fcsr0) & flags) { in update_fcsr0_mask()
77 UPDATE_FP_FLAGS(env->fcsr0, flags); in update_fcsr0_mask()
878 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in helper_set_rounding_mode()
H A Dvec_helper.c2385 UPDATE_FP_CAUSE(env->fcsr0, flags); in vec_update_fcsr0_mask()
2388 if (GET_FP_ENABLES(env->fcsr0) & flags) { in vec_update_fcsr0_mask()
2391 UPDATE_FP_FLAGS(env->fcsr0, flags); in vec_update_fcsr0_mask()
2402 SET_FP_CAUSE(env->fcsr0, 0); in vec_clear_cause()
/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c487 env->fcsr0 = fpu.fcsr; in kvm_loongarch_get_regs_fp()
508 fpu.fcsr = env->fcsr0; in kvm_loongarch_put_regs_fp()
/openbmc/linux/arch/loongarch/
H A DKconfig257 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)