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Searched refs:fVSATW (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h309 #define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V)))
310 #define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31))
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc32 #define fVSATW(A) fVSATN(32, fCAST8_8s(A))
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef560 VdV.w[i] = fVSATW(accum))
567 VxV.w[i] = fVSATW(VxV.w[i]+accum))
577 VdV.w[i] = fVSATW(accum))
584 VxV.w[i] = fVSATW(accum))
594 VdV.w[i] = fVSATW(accum))
601 VxV.w[i] = fVSATW(accum))
615 VdV.w[i] = fVSATW(accum))
622 VxV.w[i] = fVSATW(accum))
631 VdV.w[i] = fVSATW(accum))
638 VxV.w[i] = fVSATW(accum))
[all …]
H A Dmacros.def740 fVSATW( ( ( ((long long)U)<<32 ) | fZXTN(32,64,V) ) ),
745 fVSATW(((U)<<1) | ((V)>>31)),
/openbmc/qemu/target/hexagon/
H A Dmacros.h472 #define fVSATW(A) fVSATN(32, ((long long)A)) macro
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def942 fVSATW, /* saturating to 32-bits*/