| /openbmc/linux/arch/x86/kvm/ |
| H A D | pmu.c | 319 static bool filter_contains_match(u64 *events, u64 nevents, u64 eventsel) in filter_contains_match() argument
321 u64 event_select = eventsel & kvm_pmu_ops.EVENTSEL_EVENT; in filter_contains_match()
322 u64 umask = eventsel & ARCH_PERFMON_EVENTSEL_UMASK; in filter_contains_match()
353 u64 eventsel) in is_gp_event_allowed() argument
355 if (filter_contains_match(f->includes, f->nr_includes, eventsel) && in is_gp_event_allowed()
356 !filter_contains_match(f->excludes, f->nr_excludes, eventsel)) in is_gp_event_allowed()
387 return is_gp_event_allowed(filter, pmc->eventsel); in check_pmu_event_filter()
402 u64 eventsel = pmc->eventsel; in reprogram_counter() local
403 u64 new_config = eventsel; in reprogram_counter()
414 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) in reprogram_counter()
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| H A D | pmu.h | 158 return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; in pmc_speculative_in_use()
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| /openbmc/linux/arch/x86/kvm/vmx/ |
| H A D | pmu_intel.c | 51 u8 eventsel; member
107 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; in intel_hw_event_available()
108 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; in intel_hw_event_available()
118 if (intel_arch_events[i].eventsel != event_select || in intel_hw_event_available()
380 msr_info->data = pmc->eventsel; in intel_pmu_get_msr()
454 if (data != pmc->eventsel) { in intel_pmu_set_msr()
455 pmc->eventsel = data; in intel_pmu_set_msr()
480 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) | in setup_fixed_pmc_eventsel()
481 intel_arch_events[event].eventsel; in setup_fixed_pmc_eventsel()
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| /openbmc/linux/arch/x86/kvm/svm/ |
| H A D | pmu.c | 146 msr_info->data = pmc->eventsel; in amd_pmu_get_msr()
171 if (data != pmc->eventsel) { in amd_pmu_set_msr()
172 pmc->eventsel = data; in amd_pmu_set_msr()
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| /openbmc/linux/arch/arm64/kvm/ |
| H A D | pmu-emul.c | 585 u64 eventsel, reg, data; in kvm_pmu_create_perf_event() local
592 eventsel = ARMV8_PMUV3_PERFCTR_CPU_CYCLES; in kvm_pmu_create_perf_event()
594 eventsel = data & kvm_pmu_event_mask(vcpu->kvm); in kvm_pmu_create_perf_event()
600 if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR || in kvm_pmu_create_perf_event()
601 eventsel == ARMV8_PMUV3_PERFCTR_CHAIN) in kvm_pmu_create_perf_event()
609 !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) in kvm_pmu_create_perf_event()
621 attr.config = eventsel; in kvm_pmu_create_perf_event()
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| /openbmc/linux/arch/x86/events/amd/ |
| H A D | core.c | 300 static inline int amd_pmu_addr_offset(int index, bool eventsel) in amd_pmu_addr_offset() argument
307 if (eventsel) in amd_pmu_addr_offset()
320 if (eventsel) in amd_pmu_addr_offset()
1271 .eventsel = MSR_K7_EVNTSEL0,
1373 x86_pmu.eventsel = MSR_F15H_PERF_CTL; in amd_core_pmu_init()
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | df_v3_6.c | 412 uint32_t eventsel, instance, unitmask; in df_v3_6_pmc_get_ctrl_settings() local
424 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; in df_v3_6_pmc_get_ctrl_settings()
432 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel; in df_v3_6_pmc_get_ctrl_settings()
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| /openbmc/linux/arch/x86/events/intel/ |
| H A D | p6.c | 210 .eventsel = MSR_P6_EVNTSEL0,
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| H A D | knc.c | 299 .eventsel = MSR_KNC_EVNTSEL0,
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| H A D | p4.c | 1345 .eventsel = MSR_P4_BPU_CCCR0,
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| H A D | core.c | 4943 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4996 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
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| /openbmc/linux/arch/x86/events/ |
| H A D | perf_event.h | 758 unsigned eventsel; member
760 int (*addr_offset)(int index, bool eventsel);
1098 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
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| /openbmc/linux/arch/x86/events/zhaoxin/ |
| H A D | core.c | 468 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | kvm_host.h | 497 u64 eventsel; member
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