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/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_eqs.c27 #define GET_EQ_NUM_PAGES(eq, pg_size) \ argument
28 (ALIGN((eq)->q_len * (eq)->elem_size, pg_size) / (pg_size))
30 #define GET_EQ_NUM_ELEMS_IN_PG(eq, pg_size) ((pg_size) / (eq)->elem_size) argument
32 #define EQ_CONS_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
33 HINIC_CSR_AEQ_CONS_IDX_ADDR((eq)->q_id) : \
34 HINIC_CSR_CEQ_CONS_IDX_ADDR((eq)->q_id))
36 #define EQ_PROD_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
37 HINIC_CSR_AEQ_PROD_IDX_ADDR((eq)->q_id) : \
38 HINIC_CSR_CEQ_PROD_IDX_ADDR((eq)->q_id))
40 #define EQ_HI_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \ argument
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Deq.c94 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) in mlx5_eq_cq_get() argument
96 struct mlx5_cq_table *table = &eq->cq_table; in mlx5_eq_cq_get()
114 struct mlx5_eq *eq = &eq_comp->core; in mlx5_eq_comp_int() local
119 eqe = next_eqe_sw(eq); in mlx5_eq_comp_int()
133 cq = mlx5_eq_cq_get(eq, cqn); in mlx5_eq_comp_int()
139 dev_dbg_ratelimited(eq->dev->device, in mlx5_eq_comp_int()
143 ++eq->cons_index; in mlx5_eq_comp_int()
145 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq))); in mlx5_eq_comp_int()
148 eq_update_ci(eq, 1); in mlx5_eq_comp_int()
161 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq) in mlx5_eq_poll_irq_disabled() argument
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/openbmc/linux/drivers/infiniband/hw/erdma/
H A Derdma_eq.c11 void notify_eq(struct erdma_eq *eq) in notify_eq() argument
13 u64 db_data = FIELD_PREP(ERDMA_EQDB_CI_MASK, eq->ci) | in notify_eq()
16 *eq->db_record = db_data; in notify_eq()
17 writeq(db_data, eq->db); in notify_eq()
19 atomic64_inc(&eq->notify_num); in notify_eq()
22 void *get_next_valid_eqe(struct erdma_eq *eq) in get_next_valid_eqe() argument
24 u64 *eqe = get_queue_entry(eq->qbuf, eq->ci, eq->depth, EQE_SHIFT); in get_next_valid_eqe()
27 return owner ^ !!(eq->ci & eq->depth) ? eqe : NULL; in get_next_valid_eqe()
85 struct erdma_eq *eq = &dev->aeq; in erdma_aeq_init() local
88 eq->depth = ERDMA_DEFAULT_EQ_DEPTH; in erdma_aeq_init()
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/openbmc/linux/sound/pci/au88x0/
H A Dau88x0_eq.c56 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftCoefs()
78 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightCoefs()
101 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftStates()
118 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightStates()
164 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetBypassGain()
211 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsTarget()
221 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsTarget()
231 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsCurrent()
241 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsCurrent()
252 eqhw_t *eqhw = &(vortex->eq.this04);
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/openbmc/linux/drivers/infiniband/hw/mthca/
H A Dmthca_eq.c173 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in tavor_set_eq_ci() argument
184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci()
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in arbel_set_eq_ci() argument
194 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); in arbel_set_eq_ci()
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in set_eq_ci() argument
202 arbel_set_eq_ci(dev, eq, ci); in set_eq_ci()
204 tavor_set_eq_ci(dev, eq, ci); in set_eq_ci()
228 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) in get_eqe() argument
230 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; in get_eqe()
231 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; in get_eqe()
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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_rst0.S11 assert eq, a5, a6
13 assert eq, a2, a6
15 assert eq, a3, a6
24 assert eq, a5, a6
26 assert eq, a2, a6
28 assert eq, a3, a6
37 assert eq, a5, a6
39 assert eq, a2, a6
41 assert eq, a3, a6
50 assert eq, a5, a6
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H A Dtest_rem.S13 assert eq, a5, a6
15 assert eq, a2, a6
17 assert eq, a4, a6
26 assert eq, a5, a6
28 assert eq, a2, a6
30 assert eq, a4, a6
39 assert eq, a5, a6
41 assert eq, a2, a6
43 assert eq, a4, a6
52 assert eq, a5, a6
[all …]
H A Dtest_quo.S13 assert eq, a5, a6
15 assert eq, a2, a6
17 assert eq, a4, a6
26 assert eq, a5, a6
28 assert eq, a2, a6
30 assert eq, a4, a6
39 assert eq, a5, a6
41 assert eq, a2, a6
43 assert eq, a4, a6
52 assert eq, a5, a6
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H A Dtest_lsc.S22 assert eq, a2, a3
25 assert eq, a2, a3
28 assert eq, a2, a3
31 assert eq, a2, a3
56 assert eq, a2, a3
59 assert eq, a4, a3
62 assert eq, a4, a3
65 assert eq, a4, a3
87 assert eq, a2, a3
90 assert eq, a2, a3
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H A Dtest_mul16.S13 assert eq, a5, a6
15 assert eq, a2, a6
17 assert eq, a3, a6
26 assert eq, a5, a6
28 assert eq, a2, a6
30 assert eq, a3, a6
39 assert eq, a5, a6
41 assert eq, a2, a6
43 assert eq, a3, a6
52 assert eq, a5, a6
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H A Dtest_phys_mem.S34 assert eq, a2, a3
36 assert eq, a2, a3
39 assert eq, a2, a3
52 assert eq, a2, a3
55 assert eq, a2, a3
58 assert eq, a2, a3
71 assert eq, a2, a3
74 assert eq, a2, a3
77 assert eq, a2, a3
90 assert eq, a2, a3
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H A Dtest_mmu.S55 assert eq, a1, a3
56 assert eq, a2, a3
61 assert eq, a1, a3
62 assert eq, a2, a3
67 assert eq, a1, a3
69 assert eq, a2, a3
92 assert eq, a2, a3
95 assert eq, a2, a3
106 assert eq, a2, a3
109 assert eq, a2, a3
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H A Dtest_sext.S11 assert eq, a3, a4
16 assert eq, a3, a4
21 assert eq, a3, a4
26 assert eq, a3, a4
31 assert eq, a3, a4
36 assert eq, a3, a4
41 assert eq, a3, a4
46 assert eq, a3, a4
51 assert eq, a3, a4
56 assert eq, a3, a4
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H A Dtest_min.S12 assert eq, a5, a4
18 assert eq, a5, a4
24 assert eq, a2, a4
30 assert eq, a3, a4
36 assert eq, a2, a4
42 assert eq, a3, a4
50 assert eq, a5, a4
56 assert eq, a5, a4
62 assert eq, a2, a4
68 assert eq, a3, a4
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H A Dtest_max.S12 assert eq, a5, a4
18 assert eq, a5, a4
24 assert eq, a2, a4
30 assert eq, a3, a4
36 assert eq, a2, a4
42 assert eq, a3, a4
50 assert eq, a5, a4
56 assert eq, a5, a4
62 assert eq, a2, a4
68 assert eq, a3, a4
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H A Dtest_windowed.S38 assert eq, a2, a3
44 assert eq, a2, a3
47 assert eq, a2, a3
55 assert eq, a2, a3
58 assert eq, a2, a3
102 assert eq, a2, a3
108 assert eq, a2, a3
111 assert eq, a2, a3
118 assert eq, a2, a3
151 assert eq, a2, a3
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H A Dtest_nsa.S11 assert eq, a3, a4
16 assert eq, a3, a4
21 assert eq, a3, a2
26 assert eq, a3, a2
31 assert eq, a3, a4
36 assert eq, a3, a4
43 assert eq, a3, a4
48 assert eq, a3, a4
53 assert eq, a3, a2
58 assert eq, a3, a2
H A Dtest_load_store.S19 assert eq, a5, a6
44 assert eq, a5, a6
50 assert eq, a6, a7
53 assert eq, a6, a7
55 assert eq, a6, a3
56 assert eq, a5, a4
75 assert eq, a5, a6
97 assert eq, a5, a6
101 assert eq, a5, a6
130 assert eq, a6, a7
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H A Dtest_mac16.S13 assert eq, a4, a5
17 assert eq, a4, a5
129 assert eq, a2, a3
132 assert eq, a3, a4
135 assert eq, a2, a3
138 assert eq, a3, a4
149 assert eq, a2, a3
152 assert eq, a3, a4
155 assert eq, a2, a3
158 assert eq, a3, a4
[all …]
H A Dtest_break.S26 assert eq, a2, a3
29 assert eq, a2, a3
32 assert eq, a2, a3
50 assert eq, a2, a3
53 assert eq, a2, a3
56 assert eq, a2, a3
89 assert eq, a2, a3
92 assert eq, a2, a3
95 assert eq, a2, a3
116 assert eq, a2, a3
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx4/
H A Deq.c97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) in eq_set_ci() argument
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
101 eq->doorbell); in eq_set_ci()
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, in get_eqe() argument
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; in get_eqe()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) in next_eqe_sw() argument
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; in mlx4_set_eq_affinity_hint() local
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Deq.h51 static inline u32 eq_get_size(struct mlx5_eq *eq) in eq_get_size() argument
53 return eq->fbc.sz_m1 + 1; in eq_get_size()
56 static inline struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) in get_eqe() argument
58 return mlx5_frag_buf_get_wqe(&eq->fbc, entry); in get_eqe()
61 static inline struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) in next_eqe_sw() argument
63 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & eq->fbc.sz_m1); in next_eqe_sw()
65 return (eqe->owner ^ (eq->cons_index >> eq->fbc.log_sz)) & 1 ? NULL : eqe; in next_eqe_sw()
68 static inline void eq_update_ci(struct mlx5_eq *eq, int arm) in eq_update_ci() argument
70 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); in eq_update_ci()
71 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); in eq_update_ci()
[all …]
/openbmc/linux/drivers/scsi/elx/efct/
H A Defct_hw_queues.c14 struct hw_eq *eq = NULL; in efct_hw_init_queues() local
34 eq = efct_hw_new_eq(hw, EFCT_HW_EQ_DEPTH); in efct_hw_init_queues()
35 if (!eq) { in efct_hw_init_queues()
40 eqs[i] = eq; in efct_hw_init_queues()
44 cq = efct_hw_new_cq(eq, in efct_hw_init_queues()
59 cq = efct_hw_new_cq(eq, hw->num_qentries[SLI4_QTYPE_CQ]); in efct_hw_init_queues()
130 struct hw_eq *eq = kzalloc(sizeof(*eq), GFP_KERNEL); in efct_hw_new_eq() local
132 if (!eq) in efct_hw_new_eq()
135 eq->type = SLI4_QTYPE_EQ; in efct_hw_new_eq()
136 eq->hw = hw; in efct_hw_new_eq()
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/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_6xx.S217 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
218 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
371 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
373 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
374 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
375 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
376 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
377 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
442 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
444 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
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/openbmc/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c64 unsigned int eq; member
130 unsigned int eq) in iproc_msi_read_reg() argument
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
139 int eq, u32 val) in iproc_msi_write_reg() argument
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
160 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) in iproc_msi_eq_offset() argument
163 return eq * EQ_MEM_REGION_SIZE; in iproc_msi_eq_offset()
165 return eq * EQ_LEN * sizeof(u32); in iproc_msi_eq_offset()
303 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) in decode_msi_hwirq() argument
309 offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); in decode_msi_hwirq()
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