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Searched refs:epc5 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/include/sound/sof/
H A Dxtensa.h29 uint32_t epc5; member
/openbmc/linux/sound/soc/sof/xtensa/
H A Dcore.c106 xoops->epc5, xoops->epc6, xoops->epc7, xoops->depc); in xtensa_dsp_oops()
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc79 XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9090 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
9093 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
9096 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc160 XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5,
H A Dxtensa-modules.c.inc11249 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
11252 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
11255 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
12388 return 167; /* xsr.epc5 */
12582 return 165; /* rsr.epc5 */
12719 return 166; /* wsr.epc5 */
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc95 XTREG(70, 280, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc11894 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
11897 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
11900 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc88 XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11263 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
11266 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
11269 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc124 XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc33407 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
33410 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
33413 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc128 XTREG( 89,420,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16516 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
16519 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
16522 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc265 XTREG(186,1864,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc75809 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
75812 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
75815 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,